filtro_fir_mac_synthesis.vhd

This sources implement a 8-bit FIR Filter with selectable coefficent rom.

    port map (
      D => registro3_M(6),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro4_M(6)
    );
  registro5_M_6 : FDCE
    port map (
      D => registro4_M(6),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro5_M(6)
    );
  registro6_M_6 : FDCE
    port map (
      D => registro5_M(6),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro6_M(6)
    );
  reg_acu_0 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(0),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(0)
    );
  reg_acu_1 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(1),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(1)
    );
  reg_acu_2 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(2),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(2)
    );
  reg_acu_3 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(3),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(3)
    );
  reg_acu_4 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(4),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(4)
    );
  reg_acu_5 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(5),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(5)
    );
  reg_acu_6 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(6),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(6)
    );
  reg_acu_7 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(7),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(7)
    );
  reg_acu_8 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(8),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(8)
    );
  reg_acu_9 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(9),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(9)
    );
  reg_acu_10 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(10),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(10)
    );
  reg_acu_11 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(11),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(11)
    );
  reg_acu_12 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(12),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(12)
    );
  reg_acu_13 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(13),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(13)
    );
  reg_acu_14 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(14),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(14)
    );
  reg_acu_15 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(15),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(15)
    );
  reg_acu_16 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(16),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(16)
    );
  reg_acu_17 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(17),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(17)
    );
  reg_acu_18 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(18),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(18)
    );
  count_aux_2 : FDC
    port map (
      D => count_aux_n0000(2),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => count_aux(2)
    );
  count_aux_Madd_n0000_Mxor_Result_1_Result1 : LUT2
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => count_aux(0),
      I1 => count_aux(1),
      O => count_aux_n0000(1)
    );
  count_aux_0 : FDC
    port map (
      D => count_aux_n0000(0),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => count_aux(0)
    );
  count_aux_1 : FDC
    port map (
      D => count_aux_n0000(1),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => count_aux(1)
    );
  Q_n00001 : LUT3
    generic map(
      INIT => X"80"
    )
    port map (
      I0 => count_aux(0),
      I1 => count_aux(1),
      I2 => count_aux(2),
      O => load
    );
  Mmult_sal_mult_inst_lut2_341 : LUT2_L
    generic map(
      INIT => X"6"
    )
    port map (
      I0 => Mmult_sal_mult_N47,
      I1 => Mmult_sal_mult_N69,
      LO => Mmult_sal_mult_inst_lut2_34
    );
  registro7_M_7 : FDCE
    port map (
      D => registro6_M(7),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro7_M(7)
    );
  registro7_M_0 : FDCE
    port map (
      D => registro6_M(0),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro7_M(0)
    );
  registro7_M_1 : FDCE
    port map (
      D => registro6_M(1),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro7_M(1)
    );
  registro7_M_2 : FDCE
    port map (
      D => registro6_M(2),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro7_M(2)
    );
  registro7_M_3 : FDCE
    port map (
      D => registro6_M(3),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro7_M(3)
    );
  registro7_M_4 : FDCE
    port map (
      D => registro6_M(4),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro7_M(4)
    );
  registro7_M_5 : FDCE
    port map (
      D => registro6_M(5),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro7_M(5)
    );
  registro6_M_7 : FDCE
    port map (
      D => registro5_M(7),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro6_M(7)
    );
  registro6_M_0 : FDCE
    port map (
      D => registro5_M(0),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro6_M(0)
    );
  registro6_M_1 : FDCE
    port map (
      D => registro5_M(1),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro6_M(1)
    );
  registro6_M_2 : FDCE
    port map (
      D => registro5_M(2),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro6_M(2)
    );
  registro6_M_3 : FDCE
    port map (
      D => registro5_M(3),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro6_M(3)
    );
  registro6_M_4 : FDCE
    port map (
      D => registro5_M(4),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro6_M(4)
    );
  registro6_M_5 : FDCE
    port map (
      D => registro5_M(5),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro6_M(5)
    );
  registro5_M_7 : FDCE
    port map (
      D => registro4_M(7),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro5_M(7)
    );
  registro5_M_0 : FDCE
    port map (
      D => registro4_M(0),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro5_M(0)
    );
  registro5_M_1 : FDCE
    port map (
      D => registro4_M(1),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro5_M(1)
    );
  registro5_M_2 : FDCE
    port map (
      D => registro4_M(2),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro5_M(2)
    );
  registro5_M_3 : FDCE
    port map (
      D => registro4_M(3),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro5_M(3)
    );
  registro5_M_4 : FDCE
    port map (
      D => registro4_M(4),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro5_M(4)
    );
  registro5_M_5 : FDCE
    port map (
      D => registro4_M(5),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro5_M(5)
    );
  registro4_M_7 : FDCE
    port map (
      D => registro3_M(7),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro4_M(7)
    );
  registro4_M_0 : FDCE
    port map (
      D => registro3_M(0),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro4_M(0)
    );
  registro4_M_1 : FDCE
    port map (
      D => registro3_M(1),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro4_M(1)
    );
  registro4_M_2 : FDCE
    port map (
      D => registro3_M(2),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro4_M(2)
    );
  registro4_M_3 : FDCE
    port map (
      D => registro3_M(3),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro4_M(3)
    );
  registro4_M_4 : FDCE
    port map (
      D => registro3_M(4),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro4_M(4)
    );
  registro4_M_5 : FDCE
    port map (
      D => registro3_M(5),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro4_M(5)
    );
  registro3_M_7 : FDCE
    port map (
      D => registro2_M(7),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro3_M(7)
    );
  registro3_M_0 : FDCE
    port map (
      D => registro2_M(0),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro3_M(0)