filtro_fir_mac_synthesis.vhd

This sources implement a 8-bit FIR Filter with selectable coefficent rom.

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-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.38
--  \   \         Application: netgen
--  /   /         Filename: filtro_fir_mac_synthesis.vhd
-- /___/   /\     Timestamp: Thu Jan 15 11:25:24 2009
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command: -intstyle ise -ar Structure -w -ofmt vhdl -sim filtro_fir_mac.ngc filtro_fir_mac_synthesis.vhd 
-- Device: xc2s200e-6-pq208
-- Design Name: filtro_fir_mac
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity filtro_fir_mac is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    entrada : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    salida : out STD_LOGIC_VECTOR ( 19 downto 0 ) 
  );
end filtro_fir_mac;

architecture Structure of filtro_fir_mac is
  signal clk_BUFGP : STD_LOGIC; 
  signal reset_IBUF : STD_LOGIC; 
  signal load : STD_LOGIC; 
  signal entrada_7_IBUF : STD_LOGIC; 
  signal entrada_6_IBUF : STD_LOGIC; 
  signal entrada_5_IBUF : STD_LOGIC; 
  signal entrada_4_IBUF : STD_LOGIC; 
  signal entrada_3_IBUF : STD_LOGIC; 
  signal entrada_2_IBUF : STD_LOGIC; 
  signal entrada_1_IBUF : STD_LOGIC; 
  signal entrada_0_IBUF : STD_LOGIC; 
  signal sal_mult_1_Q : STD_LOGIC; 
  signal sal_mult_3_Q : STD_LOGIC; 
  signal sal_mult_5_Q : STD_LOGIC; 
  signal sal_mult_6_Q : STD_LOGIC; 
  signal sal_mult_7_Q : STD_LOGIC; 
  signal sal_mult_8_Q : STD_LOGIC; 
  signal sal_mult_9_Q : STD_LOGIC; 
  signal sal_mult_10_Q : STD_LOGIC; 
  signal sal_mult_11_Q : STD_LOGIC; 
  signal sal_mult_12_Q : STD_LOGIC; 
  signal sal_mult_13_Q : STD_LOGIC; 
  signal sal_mult_14_Q : STD_LOGIC; 
  signal sal_mult_15_Q : STD_LOGIC; 
  signal salida_rom_0_Q : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_28 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_54 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_29 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_55 : STD_LOGIC; 
  signal salida_rom_5_Q : STD_LOGIC; 
  signal Mmult_sal_mult_N70 : STD_LOGIC; 
  signal salida_rom_7_Q : STD_LOGIC; 
  signal N0 : STD_LOGIC; 
  signal Mmult_sal_mult_N69 : STD_LOGIC; 
  signal reset_IBUF_1 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_18 : STD_LOGIC; 
  signal MUX_BLOCK_N3 : STD_LOGIC; 
  signal MUX_BLOCK_N2 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_16 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_15 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_43 : STD_LOGIC; 
  signal MUX_BLOCK_N01 : STD_LOGIC; 
  signal MUX_BLOCK_N11 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF5 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF515 : STD_LOGIC; 
  signal MUX_BLOCK_N31 : STD_LOGIC; 
  signal MUX_BLOCK_N30 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF514 : STD_LOGIC; 
  signal MUX_BLOCK_N29 : STD_LOGIC; 
  signal MUX_BLOCK_N28 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF513 : STD_LOGIC; 
  signal MUX_BLOCK_N27 : STD_LOGIC; 
  signal MUX_BLOCK_N26 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF512 : STD_LOGIC; 
  signal MUX_BLOCK_N25 : STD_LOGIC; 
  signal MUX_BLOCK_N24 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF511 : STD_LOGIC; 
  signal MUX_BLOCK_N23 : STD_LOGIC; 
  signal MUX_BLOCK_N22 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF510 : STD_LOGIC; 
  signal MUX_BLOCK_N21 : STD_LOGIC; 
  signal MUX_BLOCK_N20 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF59 : STD_LOGIC; 
  signal MUX_BLOCK_N19 : STD_LOGIC; 
  signal MUX_BLOCK_N18 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF58 : STD_LOGIC; 
  signal MUX_BLOCK_N17 : STD_LOGIC; 
  signal MUX_BLOCK_N16 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF57 : STD_LOGIC; 
  signal MUX_BLOCK_N15 : STD_LOGIC; 
  signal MUX_BLOCK_N14 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF56 : STD_LOGIC; 
  signal MUX_BLOCK_N13 : STD_LOGIC; 
  signal MUX_BLOCK_N12 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF55 : STD_LOGIC; 
  signal MUX_BLOCK_N111 : STD_LOGIC; 
  signal MUX_BLOCK_N10 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF54 : STD_LOGIC; 
  signal MUX_BLOCK_N9 : STD_LOGIC; 
  signal MUX_BLOCK_N8 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF53 : STD_LOGIC; 
  signal MUX_BLOCK_N7 : STD_LOGIC; 
  signal MUX_BLOCK_N6 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF52 : STD_LOGIC; 
  signal MUX_BLOCK_N5 : STD_LOGIC; 
  signal MUX_BLOCK_N4 : STD_LOGIC; 
  signal MUX_BLOCK_count_aux_1_mmx_out1_count_aux_1_mmx_out1_MUXF51 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_0_cyo : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_1_cyo : STD_LOGIC; 
  signal N5 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_2_cyo : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_3_cyo : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_4_cyo : STD_LOGIC; 
  signal N8 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_5_cyo : STD_LOGIC; 
  signal N9 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_6_cyo : STD_LOGIC; 
  signal N10 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_7_cyo : STD_LOGIC; 
  signal N11 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_8_cyo : STD_LOGIC; 
  signal N12 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_9_cyo : STD_LOGIC; 
  signal N13 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_10_cyo : STD_LOGIC; 
  signal N14 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_11_cyo : STD_LOGIC; 
  signal N15 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_12_cyo : STD_LOGIC; 
  signal N16 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_13_cyo : STD_LOGIC; 
  signal N17 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_14_cyo : STD_LOGIC; 
  signal N18 : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_15_cyo : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_16_cyo : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_17_cyo : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_18_cyo : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_57 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_32 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_58 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_33 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_59 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_34 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_60 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_35 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_30 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_53 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_26 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_52 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_25 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_51 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_24 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_50 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_23 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_49 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_22 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_48 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_21 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_47 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_20 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_46 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_61 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_36 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_62 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_37 : STD_LOGIC; 
  signal Mmult_sal_mult_N68 : STD_LOGIC; 
  signal Mmult_sal_mult_N67 : STD_LOGIC; 
  signal Mmult_sal_mult_N66 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_45 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_0 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_0 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_0 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_39 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_0 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_1 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_1 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_64 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_1 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_2 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_2 : STD_LOGIC; 
  signal Mmult_sal_mult_N3 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_2 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_3 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_3 : STD_LOGIC; 
  signal Mmult_sal_mult_N4 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_3 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_4 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_4 : STD_LOGIC; 
  signal Mmult_sal_mult_N5 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_4 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_5 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_5 : STD_LOGIC; 
  signal Mmult_sal_mult_N6 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_5 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_6 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_6 : STD_LOGIC; 
  signal Mmult_sal_mult_N7 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_6 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_7 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_7 : STD_LOGIC; 
  signal Mmult_sal_mult_N8 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_1 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_8 : STD_LOGIC; 
  signal Mmult_sal_mult_N9 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_2 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_8 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_9 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_7 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_9 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_10 : STD_LOGIC; 
  signal Mmult_sal_mult_N11 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_8 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_10 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_11 : STD_LOGIC; 
  signal Mmult_sal_mult_N12 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_9 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_11 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_12 : STD_LOGIC; 
  signal Mmult_sal_mult_N13 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_10 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_12 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_13 : STD_LOGIC; 
  signal Mmult_sal_mult_N14 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_11 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_13 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_14 : STD_LOGIC; 
  signal Mmult_sal_mult_N15 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_12 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_14 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_15 : STD_LOGIC; 
  signal Mmult_sal_mult_N16 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_13 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_15 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_16 : STD_LOGIC; 
  signal Mmult_sal_mult_N17 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_3 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_17 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_19 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_4 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_16 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_18 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_14 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_17 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_19 : STD_LOGIC; 
  signal Mmult_sal_mult_N20 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_15 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_18 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_20 : STD_LOGIC; 
  signal Mmult_sal_mult_N21 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_16 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_19 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_21 : STD_LOGIC; 
  signal Mmult_sal_mult_N22 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_17 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_20 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_22 : STD_LOGIC; 
  signal Mmult_sal_mult_N23 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_18 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_21 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_23 : STD_LOGIC; 
  signal Mmult_sal_mult_N24 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_19 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_22 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_24 : STD_LOGIC; 
  signal Mmult_sal_mult_N25 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_20 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_23 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_25 : STD_LOGIC; 
  signal Mmult_sal_mult_N26 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_5 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_26 : STD_LOGIC; 
  signal Mmult_sal_mult_N27 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_6 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_24 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_27 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_21 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_25 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_28 : STD_LOGIC; 
  signal Mmult_sal_mult_N29 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_22 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_26 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_29 : STD_LOGIC; 
  signal Mmult_sal_mult_N30 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_23 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_27 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_30 : STD_LOGIC; 
  signal Mmult_sal_mult_N31 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_24 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_28 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_31 : STD_LOGIC; 
  signal Mmult_sal_mult_N32 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_25 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_29 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_32 : STD_LOGIC; 
  signal Mmult_sal_mult_N33 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_26 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_30 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_33 : STD_LOGIC; 
  signal Mmult_sal_mult_N34 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut4_27 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_multand_31 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_34 : STD_LOGIC; 
  signal Mmult_sal_mult_N35 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_7 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_35 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_56 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_44 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_31 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_38 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_63 : STD_LOGIC; 
  signal Mmult_sal_mult_N41 : STD_LOGIC; 
  signal Mmult_sal_mult_N42 : STD_LOGIC; 
  signal Mmult_sal_mult_N43 : STD_LOGIC; 
  signal Mmult_sal_mult_N44 : STD_LOGIC; 
  signal Mmult_sal_mult_N45 : STD_LOGIC; 
  signal Mmult_sal_mult_N46 : STD_LOGIC; 
  signal Mmult_sal_mult_N47 : STD_LOGIC; 
  signal Mmult_sal_mult_N48 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_8 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_36 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_9 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_37 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_10 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_38 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_11 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_39 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_12 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_40 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_13 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_41 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_14 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_cy_42 : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_36_rt : STD_LOGIC; 
  signal reg_acu_16_rt : STD_LOGIC; 
  signal reg_acu_17_rt : STD_LOGIC; 
  signal reg_acu_18_rt : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_38_rt : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_16_rt : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_37_rt : STD_LOGIC; 
  signal Mmult_sal_mult_inst_lut2_26_rt : STD_LOGIC; 
  signal count_aux_0_1 : STD_LOGIC; 
  signal count_aux_1_1 : STD_LOGIC; 
  signal salida_rom_5_1 : STD_LOGIC; 
  signal count_aux_02 : STD_LOGIC; 
  signal count_aux_1_2 : STD_LOGIC; 
  signal salida_rom_5_1_1 : STD_LOGIC; 
  signal count_aux_0_3 : STD_LOGIC; 
  signal count_aux_0_4 : STD_LOGIC; 
  signal N141 : STD_LOGIC; 
  signal N151 : STD_LOGIC; 
  signal count_aux : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal registro0_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal sal_sum : STD_LOGIC_VECTOR ( 19 downto 0 ); 
  signal registro4_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal registro3_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal registro_salida_M : STD_LOGIC_VECTOR ( 19 downto 0 ); 
  signal registro5_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal registro6_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal registro7_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal registro1_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal sal_mux : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal reg_acu : STD_LOGIC_VECTOR ( 19 downto 0 ); 
  signal registro2_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal count_aux_n0000 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
begin
  salida_rom_0_1 : LUT3
    generic map(
      INIT => X"91"
    )
    port map (
      I0 => count_aux_02,
      I1 => count_aux_1_2,
      I2 => count_aux(2),
      O => salida_rom_0_Q
    );
  filtro_fir_mac_sal_sum_19_xor : XORCY
    port map (
      CI => filtro_fir_mac_sal_sum_18_cyo,
      LI => reg_acu(19),
      O => sal_sum(19)
    );
  Mmult_sal_mult_inst_cy_62_0 : MUXCY
    port map (
      CI => Mmult_sal_mult_inst_cy_61,
      DI => N0,
      S => Mmult_sal_mult_inst_lut2_36_rt,
      O => Mmult_sal_mult_inst_cy_62
    );
  XST_GND : GND
    port map (
      G => N0
    );
  salida_rom_7_1 : LUT3_D
    generic map(
      INIT => X"89"
    )
    port map (
      I0 => count_aux(0),
      I1 => count_aux(1),
      I2 => count_aux(2),
      LO => N141,
      O => salida_rom_7_Q
    );
  registro_salida_M_18 : FDCE
    port map (
      D => sal_sum(18),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro_salida_M(18)
    );
  registro7_M_6 : FDCE
    port map (
      D => registro6_M(6),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro7_M(6)
    );
  count_aux_Madd_n0000_n00061_INV_0 : INV
    port map (
      I => count_aux(0),
      O => count_aux_n0000(0)
    );
  reg_acu_19 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => sal_sum(19),
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => reg_acu(19)
    );
  reset_IBUF_1_1 : BUF
    port map (
      I => reset_IBUF,
      O => reset_IBUF_1
    );
  registro0_M_6 : FDCE
    port map (
      D => entrada_6_IBUF,
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro0_M(6)
    );
  registro1_M_6 : FDCE
    port map (
      D => registro0_M(6),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro1_M(6)
    );
  registro2_M_6 : FDCE
    port map (
      D => registro1_M(6),
      CE => load,
      CLR => reset_IBUF,
      C => clk_BUFGP,
      Q => registro2_M(6)
    );
  registro3_M_6 : FDCE
    port map (
      D => registro2_M(6),
      CE => load,
      CLR => reset_IBUF_1,
      C => clk_BUFGP,
      Q => registro3_M(6)
    );
  registro4_M_6 : FDCE