retail de vhdl.txt

来自「This sources implement a 8-bit FIR Filte」· 文本 代码 · 共 51 行

entity filtro is					--Generic sirve para definir constantes...
port( 	clk	in	std_logic
	reset	in	std_logic
	din	in	std_logic_vector
	dout	out 	std_logic_vector
	)

use ieee.numeric_std.all

Generic(datadata_width: integer :=8;
	taps: integer := 8;
	cnt_bits: integer := 3;
	)

signal coef std_logic_vector( downto 0)
signal prod (2*data_width-1 downto 0)
signal sum 
signal sum_acu

prod<= signed(data)*signed(coef) //linea del multiplicador

data<= data(to_integer(unsigned(address)));

sum <= prod + sum_acu;

process ()
begin
	if(reset = '1') then 
		sum_acu <= (others=>'0');
	elseif (clk_event and clk='1')
		if(addres="111") then
			sum_acu <= (others=>'0');
	else 
		sum_acu<= sum;
	end if;

end process;

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entity cnt
architecture
signal count_aux: unsigned(n-1 downto 0)
begin
   process(clk,reset)
   begin
      if(reset=