transcript

This sources implement a 8-bit FIR Filter with selectable coefficent rom.

# Reading C:/Modeltech_pe_edu_6.5a/tcl/vsim/pref.tcl 
# do sim1_vhd.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim PE Student Edition vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity c_rom_1
# -- Compiling architecture behavioral of c_rom_1
# Model Technology ModelSim PE Student Edition vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity c_rom_2
# -- Compiling architecture behavioral of c_rom_2
# Model Technology ModelSim PE Student Edition vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity c_rom_3
# -- Compiling architecture behavioral of c_rom_3
# Model Technology ModelSim PE Student Edition vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity c_rom_4
# -- Compiling architecture behavioral of c_rom_4
# Model Technology ModelSim PE Student Edition vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity registro
# -- Compiling architecture behavioral of registro
# Model Technology ModelSim PE Student Edition vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Compiling entity filtro_fir_mac
# -- Compiling architecture behavioral of filtro_fir_mac
# Model Technology ModelSim PE Student Edition vcom 6.5a Compiler 2009.03 Mar 27 2009
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Loading package math_real
# -- Compiling entity sim1_vhd
# -- Compiling architecture behavior of sim1_vhd
# //  ModelSim PE Student Edition 6.5a Mar 28 2009 
# //
# //  Copyright 1991-2009 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# 
# // NOT FOR CORPORATE OR PRODUCTION USE.
# // THE ModelSim PE Student Edition IS NOT A SUPPORTED PRODUCT.
# // FOR HIGHER EDUCATION PURPOSES ONLY
# //
# vsim -lib work -t 1ps sim1_vhd 
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading ieee.numeric_std(body)
# Loading ieee.math_real(body)
# Loading work.sim1_vhd(behavior)
# Loading work.filtro_fir_mac(behavioral)
# Loading work.c_rom_1(behavioral)
# Loading work.c_rom_2(behavioral)
# Loading work.c_rom_3(behavioral)
# Loading work.c_rom_4(behavioral)
# Loading work.registro(behavioral)
# .main_pane.wave.interior.cs.body.pw.wf
# .main_pane.structure.interior.cs.body.struct
# .main_pane.objects.interior.cs.body
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /sim1_vhd/uut/c_4
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /sim1_vhd/uut/c_3
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /sim1_vhd/uut/c_2
# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
#    Time: 0 ps  Iteration: 0  Instance: /sim1_vhd/uut/c_1
run
# ** Error: XLOCAL <= 0.0 after reduction in SIN(X)
#    Time: 26 us  Iteration: 0  Instance: /sim1_vhd
# ** Error: XLOCAL <= 0.0 after reduction in SIN(X)
#    Time: 34 us  Iteration: 0  Instance: /sim1_vhd
# ** Error: XLOCAL <= 0.0 after reduction in SIN(X)
#    Time: 52 us  Iteration: 0  Instance: /sim1_vhd
# ** Error: XLOCAL <= 0.0 after reduction in SIN(X)
#    Time: 68 us  Iteration: 0  Instance: /sim1_vhd