filtro_fir_mac.syr

This sources implement a 8-bit FIR Filter with selectable coefficent rom.

Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Multipliers                      : 1
 8x8-bit multiplier                : 1
# Adders/Subtractors               : 1
 23-bit adder                      : 1
# Counters                         : 1
 3-bit up counter                  : 1
# Registers                        : 10
 23-bit register                   : 2
 8-bit register                    : 8
# Multiplexers                     : 6
 8-bit 4-to-1 multiplexer          : 1
 8-bit 8-to-1 multiplexer          : 5

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <filtro_fir_mac> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx/ISE.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block filtro_fir_mac, actual ratio is 2.
FlipFlop count_aux_0 has been replicated 4 time(s)
FlipFlop count_aux_1 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : filtro_fir_mac.ngr
Top Level Output File Name         : filtro_fir_mac
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 36

Macro Statistics :
# Registers                        : 11
#      23-bit register             : 2
#      3-bit register              : 1
#      8-bit register              : 8
# Multiplexers                     : 6
#      8-bit 4-to-1 multiplexer    : 1
#      8-bit 8-to-1 multiplexer    : 5
# Adders/Subtractors               : 1
#      23-bit adder                : 1
# Multipliers                      : 1
#      8x8-bit multiplier          : 1

Cell Usage :
# BELS                             : 138
#      GND                         : 1
#      INV                         : 1
#      LUT2                        : 3
#      LUT2_D                      : 1
#      LUT2_L                      : 22
#      LUT3                        : 3
#      LUT3_L                      : 32
#      LUT4                        : 7
#      MUXCY                       : 22
#      MUXF5                       : 16
#      MUXF6                       : 8
#      XORCY                       : 22
# FlipFlops/Latches                : 118
#      FDCE                        : 118
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 35
#      IBUF                        : 12
#      OBUF                        : 23
# MULTs                            : 1
#      MULT18X18                   : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400ft256-4 

 Number of Slices:                      84  out of   3584     2%  
 Number of Slice Flip Flops:           118  out of   7168     1%  
 Number of 4 input LUTs:                68  out of   7168     0%  
 Number of bonded IOBs:                 36  out of    173    20%  
 Number of MULT18X18s:                   1  out of     16     6%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 118   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 11.768ns (Maximum Frequency: 84.976MHz)
   Minimum input arrival time before clock: 12.988ns
   Maximum output required time after clock: 7.165ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 11.768ns (frequency: 84.976MHz)
  Total number of paths / destination ports: 80130 / 220
-------------------------------------------------------------------------
Delay:               11.768ns (Levels of Logic = 13)
  Source:            registro1/M_7 (FF)
  Destination:       reg_acu_22 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: registro1/M_7 to reg_acu_22
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.720   1.216  registro1/M_7 (registro1/M_7)
     LUT3_L:I0->LO         1   0.551   0.000  count_aux<0>31 (MUX_BLOCK_N31)
     MUXF5:I0->O           1   0.360   0.000  count_aux<1>_mmx_out1_count_aux<1>_mmx_out1_rn_14 (MUX_BLOCK_count_aux<1>_mmx_out1_count_aux<1>_mmx_out1_MUXF515)
     MUXF6:I0->O          11   0.342   1.144  Mmux_sal_mux_sal_mux<0>_sal_mux<0>_rn_5 (sal_mux<7>)
     MULT18X18:A7->P15     8   3.615   1.278  Mmult_sal_mult_inst_mult_0 (sal_mult<15>)
     LUT2_L:I1->LO         1   0.551   0.000  filtro_fir_mac_sal_sum<15>lut (N18)
     MUXCY:S->O            1   0.500   0.000  filtro_fir_mac_sal_sum<15>cy (filtro_fir_mac_sal_sum<15>_cyo)
     MUXCY:CI->O           1   0.064   0.000  filtro_fir_mac_sal_sum<16>cy (filtro_fir_mac_sal_sum<16>_cyo)
     MUXCY:CI->O           1   0.064   0.000  filtro_fir_mac_sal_sum<17>cy (filtro_fir_mac_sal_sum<17>_cyo)
     MUXCY:CI->O           1   0.064   0.000  filtro_fir_mac_sal_sum<18>cy (filtro_fir_mac_sal_sum<18>_cyo)
     MUXCY:CI->O           1   0.064   0.000  filtro_fir_mac_sal_sum<19>cy (filtro_fir_mac_sal_sum<19>_cyo)
     MUXCY:CI->O           1   0.064   0.000  filtro_fir_mac_sal_sum<20>cy (filtro_fir_mac_sal_sum<20>_cyo)
     MUXCY:CI->O           0   0.064   0.000  filtro_fir_mac_sal_sum<21>cy (filtro_fir_mac_sal_sum<21>_cyo)
     XORCY:CI->O           2   0.904   0.000  filtro_fir_mac_sal_sum<22>_xor (sal_sum<22>)
     FDCE:D                    0.203          reg_acu_22
    ----------------------------------------
    Total                     11.768ns (8.130ns logic, 3.638ns route)
                                       (69.1% logic, 30.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 8903 / 85
-------------------------------------------------------------------------
Offset:              12.988ns (Levels of Logic = 13)
  Source:            sel<1> (PAD)
  Destination:       reg_acu_22 (FF)
  Destination Clock: clk rising

  Data Path: sel<1> to reg_acu_22
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.821   1.256  sel_1_IBUF (sel_1_IBUF)
     LUT2:I0->O            4   0.551   1.256  sal_mux_coef<1>1 (N40)
     LUT4:I0->O           12   0.551   1.118  sal_mux_coef<7>2 (sal_mux_coef<7>)
     MULT18X18:B7->P15     8   3.615   1.278  Mmult_sal_mult_inst_mult_0 (sal_mult<15>)
     LUT2_L:I1->LO         1   0.551   0.000  filtro_fir_mac_sal_sum<15>lut (N18)
     MUXCY:S->O            1   0.500   0.000  filtro_fir_mac_sal_sum<15>cy (filtro_fir_mac_sal_sum<15>_cyo)
     MUXCY:CI->O           1   0.064   0.000  filtro_fir_mac_sal_sum<16>cy (filtro_fir_mac_sal_sum<16>_cyo)
     MUXCY:CI->O           1   0.064   0.000  filtro_fir_mac_sal_sum<17>cy (filtro_fir_mac_sal_sum<17>_cyo)
     MUXCY:CI->O           1   0.064   0.000  filtro_fir_mac_sal_sum<18>cy (filtro_fir_mac_sal_sum<18>_cyo)
     MUXCY:CI->O           1   0.064   0.000  filtro_fir_mac_sal_sum<19>cy (filtro_fir_mac_sal_sum<19>_cyo)
     MUXCY:CI->O           1   0.064   0.000  filtro_fir_mac_sal_sum<20>cy (filtro_fir_mac_sal_sum<20>_cyo)
     MUXCY:CI->O           0   0.064   0.000  filtro_fir_mac_sal_sum<21>cy (filtro_fir_mac_sal_sum<21>_cyo)
     XORCY:CI->O           2   0.904   0.000  filtro_fir_mac_sal_sum<22>_xor (sal_sum<22>)
     FDCE:D                    0.203          reg_acu_22
    ----------------------------------------
    Total                     12.988ns (8.080ns logic, 4.908ns route)
                                       (62.2% logic, 37.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 23 / 23
-------------------------------------------------------------------------
Offset:              7.165ns (Levels of Logic = 1)
  Source:            registro_salida/M_22 (FF)
  Destination:       salida<22> (PAD)
  Source Clock:      clk rising

  Data Path: registro_salida/M_22 to salida<22>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             1   0.720   0.801  registro_salida/M_22 (registro_salida/M_22)
     OBUF:I->O                 5.644          salida_22_OBUF (salida<22>)
    ----------------------------------------
    Total                      7.165ns (6.364ns logic, 0.801ns route)
                                       (88.8% logic, 11.2% route)

=========================================================================
CPU : 6.17 / 6.72 s | Elapsed : 6.00 / 6.00 s
 
--> 

Total memory usage is 117040 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    2 (   0 filtered)