filtro_fir_mac.syr

This sources implement a 8-bit FIR Filter with selectable coefficent rom.

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: filtro_fir_mac.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "filtro_fir_mac.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "filtro_fir_mac"
Output Format                      : NGC
Target Device                      : xc3s400-4-ft256

---- Source Options
Top Module Name                    : filtro_fir_mac
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : filtro_fir_mac.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/c_rom_1.vhd" in Library work.
Architecture behavioral of Entity c_rom_1 is up to date.
Compiling vhdl file "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/c_rom_2.vhd" in Library work.
Entity <c_rom_2> compiled.
Entity <c_rom_2> (Architecture <behavioral>) compiled.
Compiling vhdl file "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/c_rom_3.vhd" in Library work.
Architecture behavioral of Entity c_rom_3 is up to date.
Compiling vhdl file "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/c_rom_4.vhd" in Library work.
Architecture behavioral of Entity c_rom_4 is up to date.
Compiling vhdl file "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/registro.vhd" in Library work.
Architecture behavioral of Entity registro is up to date.
Compiling vhdl file "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/filtro_fir_mac.vhd" in Library work.
Architecture behavioral of Entity filtro_fir_mac is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <filtro_fir_mac> (Architecture <behavioral>).
INFO:Xst:1561 - "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/filtro_fir_mac.vhd" line 182: Mux is complete : default of case is discarded
INFO:Xst:1561 - "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/filtro_fir_mac.vhd" line 199: Mux is complete : default of case is discarded
Entity <filtro_fir_mac> analyzed. Unit <filtro_fir_mac> generated.

Analyzing generic Entity <c_rom_1> (Architecture <behavioral>).
	data_width = 8
	address_width = 3
	mem_depth = 8
Entity <c_rom_1> analyzed. Unit <c_rom_1> generated.

Analyzing generic Entity <c_rom_2> (Architecture <behavioral>).
	data_width = 8
	address_width = 3
	mem_depth = 8
Entity <c_rom_2> analyzed. Unit <c_rom_2> generated.

Analyzing generic Entity <c_rom_3> (Architecture <behavioral>).
	data_width = 8
	address_width = 3
	mem_depth = 8
Entity <c_rom_3> analyzed. Unit <c_rom_3> generated.

Analyzing generic Entity <c_rom_4> (Architecture <behavioral>).
	data_width = 8
	address_width = 3
	mem_depth = 8
Entity <c_rom_4> analyzed. Unit <c_rom_4> generated.

Analyzing generic Entity <registro> (Architecture <behavioral>).
	tam = 8
Entity <registro> analyzed. Unit <registro> generated.

Analyzing generic Entity <registro.0> (Architecture <behavioral>).
	tam = 23
Entity <registro.0> analyzed. Unit <registro.0> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <registro_0>.
    Related source file is "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/registro.vhd".
    Found 23-bit register for signal <M>.
    Summary:
	inferred  23 D-type flip-flop(s).
Unit <registro_0> synthesized.


Synthesizing Unit <registro>.
    Related source file is "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/registro.vhd".
    Found 8-bit register for signal <M>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <registro> synthesized.


Synthesizing Unit <c_rom_4>.
    Related source file is "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/c_rom_4.vhd".
    Found 8-bit 8-to-1 multiplexer for signal <data_out>.
    Summary:
	inferred   8 Multiplexer(s).
Unit <c_rom_4> synthesized.


Synthesizing Unit <c_rom_3>.
    Related source file is "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/c_rom_3.vhd".
    Found 8-bit 8-to-1 multiplexer for signal <data_out>.
    Summary:
	inferred   8 Multiplexer(s).
Unit <c_rom_3> synthesized.


Synthesizing Unit <c_rom_2>.
    Related source file is "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/c_rom_2.vhd".
    Found 8-bit 8-to-1 multiplexer for signal <data_out>.
    Summary:
	inferred   8 Multiplexer(s).
Unit <c_rom_2> synthesized.


Synthesizing Unit <c_rom_1>.
    Related source file is "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/c_rom_1.vhd".
    Found 8-bit 8-to-1 multiplexer for signal <data_out>.
    Summary:
	inferred   8 Multiplexer(s).
Unit <c_rom_1> synthesized.


Synthesizing Unit <filtro_fir_mac>.
    Related source file is "E:/Mis Documentos/Teleco Files/4 Teleco/1ER CUATRIMESTRE/Arquitectura de Computadores [9][AC]/Practicas/Practica 2 Filtro FIR/filtro_fir_mac.vhd".
    Found 3-bit up counter for signal <count_aux>.
    Found 23-bit register for signal <reg_acu>.
    Found 8x8-bit multiplier for signal <sal_mult>.
    Found 8-bit 8-to-1 multiplexer for signal <sal_mux>.
    Found 8-bit 4-to-1 multiplexer for signal <sal_mux_coef>.
    Found 23-bit adder for signal <sal_sum>.
    Summary:
	inferred   1 Counter(s).
	inferred  23 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
	inferred  16 Multiplexer(s).
Unit <filtro_fir_mac> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...