rom_asincrona.vhd

来自「This sources implement a 8-bit FIR Filte」· VHDL 代码 · 共 23 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity c_rom_1 is
	Generic (data_width : integer:= 8;
			 address_width : integer:= 3;
			 mem_depth : integer:= 8);

   Port ( address : in std_logic_vector(address_width-1 downto 0);
          data_out : out std_logic_vector(data_width-1 downto 0));
end c_rom_1;

architecture Behavioral of c_rom_1 is
	type rom_type is array (mem_depth-1 downto 0) of std_logic_vector(data_width-1 downto 0);
	constant rom : rom_type :=(
				"00000001", "00000010", "00000011", "00000100",
				"00000101", "00000110", "00000111", "00001000");
begin
	data_out <= rom(to_integer(unsigned(address)));

end Behavioral;