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-- Compiling entity x_iserdes
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(144368): tisd_GSR : VitalDelayType := 0.0 ps;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(144368): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(144371): tisd_SHIFTIN1 : VitalDelayType := 0.0 ps;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(144371): (vcom-1287) VITAL timing generic "tisd_shiftin1" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(144372): tisd_SHIFTIN2 : VitalDelayType := 0.0 ps;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(144372): (vcom-1287) VITAL timing generic "tisd_shiftin2" has invalid port specification.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_iserdes_v of x_iserdes
-- Compiling entity x_oddr
-- Compiling architecture x_oddr_v of x_oddr
-- Compiling entity x_plg
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146765): tisd_C23 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146765): (vcom-1287) VITAL timing generic "tisd_c23" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146766): tisd_C45 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146766): (vcom-1287) VITAL timing generic "tisd_c45" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146767): tisd_C67 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146767): (vcom-1287) VITAL timing generic "tisd_c67" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146768): tisd_GSR : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146768): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146769): tisd_RST : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146769): (vcom-1287) VITAL timing generic "tisd_rst" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146770): tisd_SEL : VitalDelayArrayType(1 downto 0) := (others => 0.000 ns);
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146770): (vcom-1287) VITAL timing generic "tisd_sel" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146779): tpw_R_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146779): (vcom-1288) VITAL timing generic "tpw_r_posedge" port specification "r" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146780): tpw_S_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146780): (vcom-1288) VITAL timing generic "tpw_s_posedge" port specification "s" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146787): trecovery_R_CLK_negedge_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146787): (vcom-1288) VITAL timing generic "trecovery_r_clk_negedge_posedge" port specification "r" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146788): trecovery_S_CLK_negedge_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146788): (vcom-1288) VITAL timing generic "trecovery_s_clk_negedge_posedge" port specification "s" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146792): tremoval_R_CLK_negedge_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146792): (vcom-1288) VITAL timing generic "tremoval_r_clk_negedge_posedge" port specification "r" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146793): tremoval_S_CLK_negedge_posedge : VitalDelayType := 0.0 ns
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(146793): (vcom-1288) VITAL timing generic "tremoval_s_clk_negedge_posedge" port specification "s" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_plg_v of x_plg
-- Compiling entity x_ioout
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147149): tisd_D1 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147149): (vcom-1287) VITAL timing generic "tisd_d1" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147150): tisd_D2 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147150): (vcom-1287) VITAL timing generic "tisd_d2" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147151): tisd_D3 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147151): (vcom-1287) VITAL timing generic "tisd_d3" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147152): tisd_D4 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147152): (vcom-1287) VITAL timing generic "tisd_d4" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147153): tisd_D5 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147153): (vcom-1287) VITAL timing generic "tisd_d5" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147154): tisd_D6 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147154): (vcom-1287) VITAL timing generic "tisd_d6" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147155): tisd_GSR : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147155): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147156): tisd_OCE : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147156): (vcom-1287) VITAL timing generic "tisd_oce" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147157): tisd_REV : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147157): (vcom-1287) VITAL timing generic "tisd_rev" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147158): tisd_SR : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147158): (vcom-1287) VITAL timing generic "tisd_sr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147159): tisd_SHIFTIN1 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147159): (vcom-1287) VITAL timing generic "tisd_shiftin1" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147160): tisd_SHIFTIN2 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(147160): (vcom-1287) VITAL timing generic "tisd_shiftin2" has invalid port specification.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_ioout_v of x_ioout
-- Compiling entity x_iot
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148176): tisd_GSR : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148176): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148177): tisd_LOAD : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148177): (vcom-1287) VITAL timing generic "tisd_load" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148178): tisd_REV : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148178): (vcom-1287) VITAL timing generic "tisd_rev" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148179): tisd_SR : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148179): (vcom-1287) VITAL timing generic "tisd_sr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148180): tisd_T1 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148180): (vcom-1287) VITAL timing generic "tisd_t1" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148181): tisd_T2 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148181): (vcom-1287) VITAL timing generic "tisd_t2" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148182): tisd_T3 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148182): (vcom-1287) VITAL timing generic "tisd_t3" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148183): tisd_T4 : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148183): (vcom-1287) VITAL timing generic "tisd_t4" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148184): tisd_TCE : VitalDelayType := 0.000 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148184): (vcom-1287) VITAL timing generic "tisd_tce" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148189): tpw_CLK_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148189): (vcom-1288) VITAL timing generic "tpw_clk_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148195): tperiod_CLK_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148195): (vcom-1288) VITAL timing generic "tperiod_clk_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148198): trecovery_GSR_CLK_negedge_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148198): (vcom-1288) VITAL timing generic "trecovery_gsr_clk_negedge_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148199): trecovery_REV_CLK_negedge_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148199): (vcom-1288) VITAL timing generic "trecovery_rev_clk_negedge_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148200): trecovery_SR_CLK_negedge_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148200): (vcom-1288) VITAL timing generic "trecovery_sr_clk_negedge_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148203): tremoval_GSR_CLK_negedge_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148203): (vcom-1288) VITAL timing generic "tremoval_gsr_clk_negedge_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148204): tremoval_REV_CLK_negedge_posedge : VitalDelayType := 0.0 ns;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148204): (vcom-1288) VITAL timing generic "tremoval_rev_clk_negedge_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148205): tremoval_SR_CLK_negedge_posedge : VitalDelayType := 0.0 ns
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148205): (vcom-1288) VITAL timing generic "tremoval_sr_clk_negedge_posedge" port specification "clk" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_iot_v of x_iot
-- Compiling entity x_oserdes
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148945): tisd_GSR : VitalDelayType := 0.0 ps;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148945): (vcom-1287) VITAL timing generic "tisd_gsr" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148948): tisd_SHIFTIN1 : VitalDelayType := 0.0 ps;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148948): (vcom-1287) VITAL timing generic "tisd_shiftin1" has invalid port specification.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148949): tisd_SHIFTIN2 : VitalDelayType := 0.0 ps;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(148949): (vcom-1287) VITAL timing generic "tisd_shiftin2" has invalid port specification.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_oserdes_v of x_oserdes
-- Compiling entity x_pmcd
-- Compiling architecture x_pmcd_v of x_pmcd
-- Compiling entity x_ramb16
-- Compiling architecture x_ramb16_v of x_ramb16
-- Compiling entity x_iddr2
-- Compiling architecture x_iddr2_v of x_iddr2
-- Compiling entity x_mult18x18sio
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(160138): tpw_C_posedge : VitalDelayType := 0 ps;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(160138): (vcom-1288) VITAL timing generic "tpw_c_posedge" port specification "c" does not denote a port.
(1076.4 section 4.3.2.1.3)
###### C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(160139): tpw_C_negedge : VitalDelayType := 0 ps;
** Warning: [6] C:\Xilinx\vhdl\src\simprims\simprim_VITAL_mti.vhd(160139): (vcom-1288) VITAL timing generic "tpw_c_negedge" port specification "c" does not denote a port.
(1076.4 section 4.3.2.1.3)
-- Compiling architecture x_mult18x18sio_v of x_mult18x18sio
-- Compiling entity x_oddr2
-- Compiling architecture x_oddr2_v of x_oddr2
"END_COMPILE<simprim>"
==============================================================================
> Log file C:\Xilinx\vhdl\mti_se\simprim\cxl_simprim.log generated > Library mapping successful, setup file(s) modelsim.ini updatedcompxlib[simprim]: No error(s), 49 warning(s)
**************************************************************************
* COMPILATION SUMMARY *
* *
* Simulator used: mti_se *
* Compiled on: Wed Jan 28 12:51:13 2009 *
* *
**************************************************************************
* Library | Lang | Mapped Name(s) | Err#(s) | Warn#(s) *
*------------------------------------------------------------------------*
* simprim | vhdl | simprim | 0 | 49 *
*------------------------------------------------------------------------*
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