filtro_fir_mac_timesim.vhd

This sources implement a 8-bit FIR Filter with selectable coefficent rom.

    )
    port map (
      I => salida_9_O,
      CTL => salida_9_ENABLE,
      O => salida(9)
    );
  salida_9_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => salida_9_ENABLE
    );
  reset_IBUF_105 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset,
      O => reset_INBUF
    );
  reset_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_INBUF,
      O => reset_IBUF
    );
  clk_BUFGP_BUFG : X_BUFGMUX
    port map (
      I0 => clk_BUFGP_IBUFG,
      I1 => GND,
      S => clk_BUFGP_BUFG_S_INVNOT,
      O => clk_BUFGP,
      GSR => GSR
    );
  clk_BUFGP_BUFG_SINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => clk_BUFGP_BUFG_S_INVNOT
    );
  Mmult_sal_mult_inst_mult_0 : X_MULT18X18
    port map (
      A(17) => sal_mux(7),
      A(16) => sal_mux(7),
      A(15) => sal_mux(7),
      A(14) => sal_mux(7),
      A(13) => sal_mux(7),
      A(12) => sal_mux(7),
      A(11) => sal_mux(7),
      A(10) => sal_mux(7),
      A(9) => sal_mux(7),
      A(8) => sal_mux(7),
      A(7) => sal_mux(7),
      A(6) => sal_mux(6),
      A(5) => sal_mux(5),
      A(4) => sal_mux(4),
      A(3) => sal_mux(3),
      A(2) => sal_mux(2),
      A(1) => sal_mux(1),
      A(0) => sal_mux(0),
      B(17) => GLOBAL_LOGIC0,
      B(16) => GLOBAL_LOGIC0,
      B(15) => GLOBAL_LOGIC0,
      B(14) => GLOBAL_LOGIC0,
      B(13) => GLOBAL_LOGIC0,
      B(12) => GLOBAL_LOGIC0,
      B(11) => GLOBAL_LOGIC0,
      B(10) => GLOBAL_LOGIC0,
      B(9) => GLOBAL_LOGIC0,
      B(8) => GLOBAL_LOGIC0,
      B(7) => GLOBAL_LOGIC0,
      B(6) => GLOBAL_LOGIC0,
      B(5) => GLOBAL_LOGIC0,
      B(4) => GLOBAL_LOGIC0,
      B(3) => salida_rom_3_0,
      B(2) => salida_rom_2_0,
      B(1) => salida_rom_1_0,
      B(0) => count_aux(0),
      P(35) => Mmult_sal_mult_inst_mult_0_PROD35,
      P(34) => Mmult_sal_mult_inst_mult_0_PROD34,
      P(33) => Mmult_sal_mult_inst_mult_0_PROD33,
      P(32) => Mmult_sal_mult_inst_mult_0_PROD32,
      P(31) => Mmult_sal_mult_inst_mult_0_PROD31,
      P(30) => Mmult_sal_mult_inst_mult_0_PROD30,
      P(29) => Mmult_sal_mult_inst_mult_0_PROD29,
      P(28) => Mmult_sal_mult_inst_mult_0_PROD28,
      P(27) => Mmult_sal_mult_inst_mult_0_PROD27,
      P(26) => Mmult_sal_mult_inst_mult_0_PROD26,
      P(25) => Mmult_sal_mult_inst_mult_0_PROD25,
      P(24) => Mmult_sal_mult_inst_mult_0_PROD24,
      P(23) => Mmult_sal_mult_inst_mult_0_PROD23,
      P(22) => Mmult_sal_mult_inst_mult_0_PROD22,
      P(21) => Mmult_sal_mult_inst_mult_0_PROD21,
      P(20) => Mmult_sal_mult_inst_mult_0_PROD20,
      P(19) => Mmult_sal_mult_inst_mult_0_PROD19,
      P(18) => Mmult_sal_mult_inst_mult_0_PROD18,
      P(17) => Mmult_sal_mult_inst_mult_0_PROD17,
      P(16) => Mmult_sal_mult_inst_mult_0_PROD16,
      P(15) => sal_mult(15),
      P(14) => sal_mult(14),
      P(13) => sal_mult(13),
      P(12) => sal_mult(12),
      P(11) => sal_mult(11),
      P(10) => sal_mult(10),
      P(9) => sal_mult(9),
      P(8) => sal_mult(8),
      P(7) => sal_mult(7),
      P(6) => sal_mult(6),
      P(5) => sal_mult(5),
      P(4) => sal_mult(4),
      P(3) => sal_mult(3),
      P(2) => sal_mult(2),
      P(1) => sal_mult(1),
      P(0) => sal_mult(0)
    );
  count_aux_2_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load,
      O => load_0
    );
  count_aux_2_DYMUX_106 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => count_aux_n0000(2),
      O => count_aux_2_DYMUX
    );
  count_aux_2_CLKINV_107 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_aux_2_CLKINV
    );
  count_aux_Madd_n0000_Mxor_Result_2_Result1 : X_LUT4
    generic map(
      INIT => X"3CCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => count_aux(2),
      ADR2 => count_aux(0),
      ADR3 => count_aux(1),
      O => count_aux_n0000(2)
    );
  registro4_M_1_DXMUX_108 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro3_M(1),
      O => registro4_M_1_DXMUX
    );
  registro4_M_1_DYMUX_109 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro3_M(0),
      O => registro4_M_1_DYMUX
    );
  registro4_M_1_SRINV_110 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => registro4_M_1_SRINV
    );
  registro4_M_1_CLKINV_111 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => registro4_M_1_CLKINV
    );
  registro4_M_1_CEINV_112 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load_0,
      O => registro4_M_1_CEINV
    );
  registro4_M_3_DXMUX_113 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro3_M(3),
      O => registro4_M_3_DXMUX
    );
  registro4_M_3_DYMUX_114 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro3_M(2),
      O => registro4_M_3_DYMUX
    );
  registro4_M_3_SRINV_115 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => registro4_M_3_SRINV
    );
  registro4_M_3_CLKINV_116 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => registro4_M_3_CLKINV
    );
  registro4_M_3_CEINV_117 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load_0,
      O => registro4_M_3_CEINV
    );
  registro4_M_5_DXMUX_118 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro3_M(5),
      O => registro4_M_5_DXMUX
    );
  registro4_M_5_DYMUX_119 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro3_M(4),
      O => registro4_M_5_DYMUX
    );
  registro4_M_5_SRINV_120 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => registro4_M_5_SRINV
    );
  registro4_M_5_CLKINV_121 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => registro4_M_5_CLKINV
    );
  registro4_M_5_CEINV_122 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load_0,
      O => registro4_M_5_CEINV
    );
  registro4_M_7_DXMUX_123 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro3_M(7),
      O => registro4_M_7_DXMUX
    );
  registro4_M_7_DYMUX_124 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro3_M(6),
      O => registro4_M_7_DYMUX
    );
  registro4_M_7_SRINV_125 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => registro4_M_7_SRINV
    );
  registro4_M_7_CLKINV_126 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => registro4_M_7_CLKINV
    );
  registro4_M_7_CEINV_127 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load_0,
      O => registro4_M_7_CEINV
    );
  salida_rom_3_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_rom(3),
      O => salida_rom_3_0
    );
  salida_rom_3_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_rom(2),
      O => salida_rom_2_0
    );
  salida_rom_2_1 : X_LUT4
    generic map(
      INIT => X"3636"
    )
    port map (
      ADR0 => count_aux_1_1,
      ADR1 => count_aux(2),
      ADR2 => count_aux(0),
      ADR3 => VCC,
      O => salida_rom(2)
    );
  registro5_M_1_DXMUX_128 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro4_M(1),
      O => registro5_M_1_DXMUX
    );
  registro5_M_1_DYMUX_129 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro4_M(0),
      O => registro5_M_1_DYMUX
    );
  registro5_M_1_SRINV_130 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => registro5_M_1_SRINV
    );
  registro5_M_1_CLKINV_131 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => registro5_M_1_CLKINV
    );
  registro5_M_1_CEINV_132 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load_0,
      O => registro5_M_1_CEINV
    );
  MUX_BLOCK_c_rom_Mmux_data_out_salida_rom_1_MUXF51_F5USED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => MUX_BLOCK_c_rom_Mmux_data_out_salida_rom_1_MUXF51_F5MUX,
      O => MUX_BLOCK_c_rom_Mmux_data_out_salida_rom_1_MUXF51
    );
  MUX_BLOCK_c_rom_Mmux_data_out_salida_rom_1_MUXF51_F5MUX_133 : X_MUX2
    port map (
      IA => c_rom_Mmux_data_out_salida_rom_0_3_O,
      IB => c_rom_Mmux_data_out_salida_rom_0_2_O,
      SEL => MUX_BLOCK_c_rom_Mmux_data_out_salida_rom_1_MUXF51_BXINV,
      O => MUX_BLOCK_c_rom_Mmux_data_out_salida_rom_1_MUXF51_F5MUX
    );
  MUX_BLOCK_c_rom_Mmux_data_out_salida_rom_1_MUXF51_BXINV_134 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => count_aux_1_1,
      O => MUX_BLOCK_c_rom_Mmux_data_out_salida_rom_1_MUXF51_BXINV
    );
  clk_BUFGP_IBUFG_135 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk,
      O => clk_INBUF
    );
  clk_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_INBUF,
      O => clk_BUFGP_IBUFG
    );
  entrada_0_IBUF : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => entrada(0),
      O => entrada_0_INBUF
    );
  entrada_0_IFF_IFFDMUX_136 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => entrada_0_INBUF,
      O => entrada_0_IFF_IFFDMUX