filtro_fir_mac_timesim.vhd

This sources implement a 8-bit FIR Filter with selectable coefficent rom.

    port map (
      I => load_0,
      O => registro1_M_3_CEINV
    );
  registro1_M_5_DXMUX_75 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro0_M(5),
      O => registro1_M_5_DXMUX
    );
  registro1_M_5_DYMUX_76 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro0_M(4),
      O => registro1_M_5_DYMUX
    );
  registro1_M_5_SRINV_77 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => registro1_M_5_SRINV
    );
  registro1_M_5_CLKINV_78 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => registro1_M_5_CLKINV
    );
  registro1_M_5_CEINV_79 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load_0,
      O => registro1_M_5_CEINV
    );
  registro1_M_7_DXMUX_80 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro0_M(7),
      O => registro1_M_7_DXMUX
    );
  registro1_M_7_DYMUX_81 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro0_M(6),
      O => registro1_M_7_DYMUX
    );
  registro1_M_7_SRINV_82 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => registro1_M_7_SRINV
    );
  registro1_M_7_CLKINV_83 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => registro1_M_7_CLKINV
    );
  registro1_M_7_CEINV_84 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load_0,
      O => registro1_M_7_CEINV
    );
  registro2_M_1_DXMUX_85 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro1_M(1),
      O => registro2_M_1_DXMUX
    );
  registro2_M_1_DYMUX_86 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro1_M(0),
      O => registro2_M_1_DYMUX
    );
  registro2_M_1_SRINV_87 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => registro2_M_1_SRINV
    );
  registro2_M_1_CLKINV_88 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => registro2_M_1_CLKINV
    );
  registro2_M_1_CEINV_89 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load_0,
      O => registro2_M_1_CEINV
    );
  count_aux_0_DXMUX_90 : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => count_aux(0),
      O => count_aux_0_DXMUX
    );
  count_aux_0_DYMUX_91 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => count_aux_0_GYMUX,
      O => count_aux_0_DYMUX
    );
  count_aux_0_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => count_aux_0_GYMUX,
      O => salida_rom_1_0
    );
  count_aux_0_GYMUX_92 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_rom(1),
      O => count_aux_0_GYMUX
    );
  count_aux_0_SRINV_93 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => count_aux_0_SRINV
    );
  count_aux_0_CLKINV_94 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_aux_0_CLKINV
    );
  registro2_M_3_DXMUX_95 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro1_M(3),
      O => registro2_M_3_DXMUX
    );
  registro2_M_3_DYMUX_96 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro1_M(2),
      O => registro2_M_3_DYMUX
    );
  registro2_M_3_SRINV_97 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => registro2_M_3_SRINV
    );
  registro2_M_3_CLKINV_98 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => registro2_M_3_CLKINV
    );
  registro2_M_3_CEINV_99 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load_0,
      O => registro2_M_3_CEINV
    );
  registro2_M_5_DXMUX_100 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro1_M(5),
      O => registro2_M_5_DXMUX
    );
  registro2_M_5_DYMUX_101 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro1_M(4),
      O => registro2_M_5_DYMUX
    );
  registro2_M_5_SRINV_102 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => registro2_M_5_SRINV
    );
  registro2_M_5_CLKINV_103 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => registro2_M_5_CLKINV
    );
  registro2_M_5_CEINV_104 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load_0,
      O => registro2_M_5_CEINV
    );
  salida_3_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_3_O,
      CTL => salida_3_ENABLE,
      O => salida(3)
    );
  salida_3_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => salida_3_ENABLE
    );
  salida_15_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_15_O,
      CTL => salida_15_ENABLE,
      O => salida(15)
    );
  salida_15_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => salida_15_ENABLE
    );
  salida_4_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_4_O,
      CTL => salida_4_ENABLE,
      O => salida(4)
    );
  salida_4_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => salida_4_ENABLE
    );
  salida_16_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_16_O,
      CTL => salida_16_ENABLE,
      O => salida(16)
    );
  salida_16_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => salida_16_ENABLE
    );
  salida_5_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_5_O,
      CTL => salida_5_ENABLE,
      O => salida(5)
    );
  salida_5_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => salida_5_ENABLE
    );
  salida_17_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_17_O,
      CTL => salida_17_ENABLE,
      O => salida(17)
    );
  salida_17_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => salida_17_ENABLE
    );
  salida_6_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_6_O,
      CTL => salida_6_ENABLE,
      O => salida(6)
    );
  salida_6_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => salida_6_ENABLE
    );
  salida_18_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_18_O,
      CTL => salida_18_ENABLE,
      O => salida(18)
    );
  salida_18_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => salida_18_ENABLE
    );
  salida_7_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_7_O,
      CTL => salida_7_ENABLE,
      O => salida(7)
    );
  salida_7_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => salida_7_ENABLE
    );
  salida_19_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_19_O,
      CTL => salida_19_ENABLE,
      O => salida(19)
    );
  salida_19_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => salida_19_ENABLE
    );
  salida_8_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => salida_8_O,
      CTL => salida_8_ENABLE,
      O => salida(8)
    );
  salida_8_ENABLEINV : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => salida_8_ENABLE
    );
  salida_9_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps