filtro_fir_mac_timesim.vhd

This sources implement a 8-bit FIR Filter with selectable coefficent rom.

  signal filtro_fir_mac_sal_sum_2_lut_O : STD_LOGIC; 
  signal registro_salida_M_2_DYMUX : STD_LOGIC; 
  signal registro_salida_M_2_XORG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_2_cyo : STD_LOGIC; 
  signal registro_salida_M_2_CYSELF : STD_LOGIC; 
  signal registro_salida_M_2_CYMUXFAST : STD_LOGIC; 
  signal registro_salida_M_2_CYAND : STD_LOGIC; 
  signal registro_salida_M_2_FASTCARRY : STD_LOGIC; 
  signal registro_salida_M_2_CYMUXG2 : STD_LOGIC; 
  signal registro_salida_M_2_CYMUXF2 : STD_LOGIC; 
  signal registro_salida_M_2_CY0G : STD_LOGIC; 
  signal registro_salida_M_2_CYSELG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_3_lut_O : STD_LOGIC; 
  signal registro_salida_M_2_SRINV : STD_LOGIC; 
  signal registro_salida_M_2_CLKINV : STD_LOGIC; 
  signal registro_salida_M_2_CEINV : STD_LOGIC; 
  signal registro_salida_M_4_DXMUX : STD_LOGIC; 
  signal registro_salida_M_4_XORF : STD_LOGIC; 
  signal registro_salida_M_4_CYINIT : STD_LOGIC; 
  signal registro_salida_M_4_CY0F : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_4_lut_O : STD_LOGIC; 
  signal registro_salida_M_4_DYMUX : STD_LOGIC; 
  signal registro_salida_M_4_XORG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_4_cyo : STD_LOGIC; 
  signal registro_salida_M_4_CYSELF : STD_LOGIC; 
  signal registro_salida_M_4_CYMUXFAST : STD_LOGIC; 
  signal registro_salida_M_4_CYAND : STD_LOGIC; 
  signal registro_salida_M_4_FASTCARRY : STD_LOGIC; 
  signal registro_salida_M_4_CYMUXG2 : STD_LOGIC; 
  signal registro_salida_M_4_CYMUXF2 : STD_LOGIC; 
  signal registro_salida_M_4_CY0G : STD_LOGIC; 
  signal registro_salida_M_4_CYSELG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_5_lut_O : STD_LOGIC; 
  signal registro_salida_M_4_SRINV : STD_LOGIC; 
  signal registro_salida_M_4_CLKINV : STD_LOGIC; 
  signal registro_salida_M_4_CEINV : STD_LOGIC; 
  signal registro_salida_M_6_DXMUX : STD_LOGIC; 
  signal registro_salida_M_6_XORF : STD_LOGIC; 
  signal registro_salida_M_6_CYINIT : STD_LOGIC; 
  signal registro_salida_M_6_CY0F : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_6_lut_O : STD_LOGIC; 
  signal registro_salida_M_6_DYMUX : STD_LOGIC; 
  signal registro_salida_M_6_XORG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_6_cyo : STD_LOGIC; 
  signal registro_salida_M_6_CYSELF : STD_LOGIC; 
  signal registro_salida_M_6_CYMUXFAST : STD_LOGIC; 
  signal registro_salida_M_6_CYAND : STD_LOGIC; 
  signal registro_salida_M_6_FASTCARRY : STD_LOGIC; 
  signal registro_salida_M_6_CYMUXG2 : STD_LOGIC; 
  signal registro_salida_M_6_CYMUXF2 : STD_LOGIC; 
  signal registro_salida_M_6_CY0G : STD_LOGIC; 
  signal registro_salida_M_6_CYSELG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_7_lut_O : STD_LOGIC; 
  signal registro_salida_M_6_SRINV : STD_LOGIC; 
  signal registro_salida_M_6_CLKINV : STD_LOGIC; 
  signal registro_salida_M_6_CEINV : STD_LOGIC; 
  signal registro_salida_M_8_DXMUX : STD_LOGIC; 
  signal registro_salida_M_8_XORF : STD_LOGIC; 
  signal registro_salida_M_8_CYINIT : STD_LOGIC; 
  signal registro_salida_M_8_CY0F : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_8_lut_O : STD_LOGIC; 
  signal registro_salida_M_8_DYMUX : STD_LOGIC; 
  signal registro_salida_M_8_XORG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_8_cyo : STD_LOGIC; 
  signal registro_salida_M_8_CYSELF : STD_LOGIC; 
  signal registro_salida_M_8_CYMUXFAST : STD_LOGIC; 
  signal registro_salida_M_8_CYAND : STD_LOGIC; 
  signal registro_salida_M_8_FASTCARRY : STD_LOGIC; 
  signal registro_salida_M_8_CYMUXG2 : STD_LOGIC; 
  signal registro_salida_M_8_CYMUXF2 : STD_LOGIC; 
  signal registro_salida_M_8_CY0G : STD_LOGIC; 
  signal registro_salida_M_8_CYSELG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_9_lut_O : STD_LOGIC; 
  signal registro_salida_M_8_SRINV : STD_LOGIC; 
  signal registro_salida_M_8_CLKINV : STD_LOGIC; 
  signal registro_salida_M_8_CEINV : STD_LOGIC; 
  signal registro_salida_M_10_DXMUX : STD_LOGIC; 
  signal registro_salida_M_10_XORF : STD_LOGIC; 
  signal registro_salida_M_10_CYINIT : STD_LOGIC; 
  signal registro_salida_M_10_CY0F : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_10_lut_O : STD_LOGIC; 
  signal registro_salida_M_10_DYMUX : STD_LOGIC; 
  signal registro_salida_M_10_XORG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_10_cyo : STD_LOGIC; 
  signal registro_salida_M_10_CYSELF : STD_LOGIC; 
  signal registro_salida_M_10_CYMUXFAST : STD_LOGIC; 
  signal registro_salida_M_10_CYAND : STD_LOGIC; 
  signal registro_salida_M_10_FASTCARRY : STD_LOGIC; 
  signal registro_salida_M_10_CYMUXG2 : STD_LOGIC; 
  signal registro_salida_M_10_CYMUXF2 : STD_LOGIC; 
  signal registro_salida_M_10_CY0G : STD_LOGIC; 
  signal registro_salida_M_10_CYSELG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_11_lut_O : STD_LOGIC; 
  signal registro_salida_M_10_SRINV : STD_LOGIC; 
  signal registro_salida_M_10_CLKINV : STD_LOGIC; 
  signal registro_salida_M_10_CEINV : STD_LOGIC; 
  signal registro_salida_M_12_DXMUX : STD_LOGIC; 
  signal registro_salida_M_12_XORF : STD_LOGIC; 
  signal registro_salida_M_12_CYINIT : STD_LOGIC; 
  signal registro_salida_M_12_CY0F : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_12_lut_O : STD_LOGIC; 
  signal registro_salida_M_12_DYMUX : STD_LOGIC; 
  signal registro_salida_M_12_XORG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_12_cyo : STD_LOGIC; 
  signal registro_salida_M_12_CYSELF : STD_LOGIC; 
  signal registro_salida_M_12_CYMUXFAST : STD_LOGIC; 
  signal registro_salida_M_12_CYAND : STD_LOGIC; 
  signal registro_salida_M_12_FASTCARRY : STD_LOGIC; 
  signal registro_salida_M_12_CYMUXG2 : STD_LOGIC; 
  signal registro_salida_M_12_CYMUXF2 : STD_LOGIC; 
  signal registro_salida_M_12_CY0G : STD_LOGIC; 
  signal registro_salida_M_12_CYSELG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_13_lut_O : STD_LOGIC; 
  signal registro_salida_M_12_SRINV : STD_LOGIC; 
  signal registro_salida_M_12_CLKINV : STD_LOGIC; 
  signal registro_salida_M_12_CEINV : STD_LOGIC; 
  signal registro_salida_M_14_DXMUX : STD_LOGIC; 
  signal registro_salida_M_14_XORF : STD_LOGIC; 
  signal registro_salida_M_14_CYINIT : STD_LOGIC; 
  signal registro_salida_M_14_CY0F : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_14_lut_O : STD_LOGIC; 
  signal registro_salida_M_14_DYMUX : STD_LOGIC; 
  signal registro_salida_M_14_XORG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_14_cyo : STD_LOGIC; 
  signal registro_salida_M_14_CYSELF : STD_LOGIC; 
  signal registro_salida_M_14_CYMUXFAST : STD_LOGIC; 
  signal registro_salida_M_14_CYAND : STD_LOGIC; 
  signal registro_salida_M_14_FASTCARRY : STD_LOGIC; 
  signal registro_salida_M_14_CYMUXG2 : STD_LOGIC; 
  signal registro_salida_M_14_CYMUXF2 : STD_LOGIC; 
  signal registro_salida_M_14_CY0G : STD_LOGIC; 
  signal registro_salida_M_14_CYSELG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_15_lut_O : STD_LOGIC; 
  signal registro_salida_M_14_SRINV : STD_LOGIC; 
  signal registro_salida_M_14_CLKINV : STD_LOGIC; 
  signal registro_salida_M_14_CEINV : STD_LOGIC; 
  signal registro_salida_M_16_DXMUX : STD_LOGIC; 
  signal registro_salida_M_16_XORF : STD_LOGIC; 
  signal registro_salida_M_16_CYINIT : STD_LOGIC; 
  signal registro_salida_M_16_CY0F : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_16_lut_O : STD_LOGIC; 
  signal registro_salida_M_16_DYMUX : STD_LOGIC; 
  signal registro_salida_M_16_XORG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_16_cyo : STD_LOGIC; 
  signal registro_salida_M_16_CYSELF : STD_LOGIC; 
  signal registro_salida_M_16_CYMUXFAST : STD_LOGIC; 
  signal registro_salida_M_16_CYAND : STD_LOGIC; 
  signal registro_salida_M_16_FASTCARRY : STD_LOGIC; 
  signal registro_salida_M_16_CYMUXG2 : STD_LOGIC; 
  signal registro_salida_M_16_CYMUXF2 : STD_LOGIC; 
  signal registro_salida_M_16_CY0G : STD_LOGIC; 
  signal registro_salida_M_16_CYSELG : STD_LOGIC; 
  signal filtro_fir_mac_sal_sum_17_lut_O : STD_LOGIC; 
  signal registro_salida_M_16_SRINV : STD_LOGIC; 
  signal registro_salida_M_16_CLKINV : STD_LOGIC; 
  signal registro_salida_M_16_CEINV : STD_LOGIC; 
  signal registro2_M_7_DXMUX : STD_LOGIC; 
  signal registro2_M_7_DYMUX : STD_LOGIC; 
  signal registro2_M_7_SRINV : STD_LOGIC; 
  signal registro2_M_7_CLKINV : STD_LOGIC; 
  signal registro2_M_7_CEINV : STD_LOGIC; 
  signal registro3_M_1_DXMUX : STD_LOGIC; 
  signal registro3_M_1_DYMUX : STD_LOGIC; 
  signal registro3_M_1_SRINV : STD_LOGIC; 
  signal registro3_M_1_CLKINV : STD_LOGIC; 
  signal registro3_M_1_CEINV : STD_LOGIC; 
  signal registro3_M_3_DXMUX : STD_LOGIC; 
  signal registro3_M_3_DYMUX : STD_LOGIC; 
  signal registro3_M_3_SRINV : STD_LOGIC; 
  signal registro3_M_3_CLKINV : STD_LOGIC; 
  signal registro3_M_3_CEINV : STD_LOGIC; 
  signal registro3_M_5_DXMUX : STD_LOGIC; 
  signal registro3_M_5_DYMUX : STD_LOGIC; 
  signal registro3_M_5_SRINV : STD_LOGIC; 
  signal registro3_M_5_CLKINV : STD_LOGIC; 
  signal registro3_M_5_CEINV : STD_LOGIC; 
  signal registro3_M_7_DXMUX : STD_LOGIC; 
  signal registro3_M_7_DYMUX : STD_LOGIC; 
  signal registro3_M_7_SRINV : STD_LOGIC; 
  signal registro3_M_7_CLKINV : STD_LOGIC; 
  signal registro3_M_7_CEINV : STD_LOGIC; 
  signal registro_salida_M_0_FFY_RST : STD_LOGIC; 
  signal registro_salida_M_0_FFX_RST : STD_LOGIC; 
  signal registro_salida_M_8_FFX_RST : STD_LOGIC; 
  signal registro_salida_M_10_FFY_RST : STD_LOGIC; 
  signal registro_salida_M_10_FFX_RST : STD_LOGIC; 
  signal registro_salida_M_12_FFY_RST : STD_LOGIC; 
  signal registro_salida_M_2_FFY_RST : STD_LOGIC; 
  signal registro_salida_M_2_FFX_RST : STD_LOGIC; 
  signal registro_salida_M_4_FFY_RST : STD_LOGIC; 
  signal registro_salida_M_4_FFX_RST : STD_LOGIC; 
  signal registro_salida_M_6_FFY_RST : STD_LOGIC; 
  signal registro_salida_M_6_FFX_RST : STD_LOGIC; 
  signal registro_salida_M_8_FFY_RST : STD_LOGIC; 
  signal registro_salida_M_12_FFX_RST : STD_LOGIC; 
  signal registro_salida_M_14_FFY_RST : STD_LOGIC; 
  signal registro_salida_M_14_FFX_RST : STD_LOGIC; 
  signal registro_salida_M_16_FFY_RST : STD_LOGIC; 
  signal registro_salida_M_16_FFX_RST : STD_LOGIC; 
  signal registro_salida_M_18_FFY_RST : STD_LOGIC; 
  signal registro_salida_M_18_FFX_RST : STD_LOGIC; 
  signal count_aux_0_3_FFY_RST : STD_LOGIC; 
  signal count_aux_0_3_FFY_RSTAND : STD_LOGIC; 
  signal count_aux_0_4_FFY_RST : STD_LOGIC; 
  signal count_aux_0_4_FFY_RSTAND : STD_LOGIC; 
  signal count_aux_1_1_FFY_RST : STD_LOGIC; 
  signal count_aux_1_1_FFY_RSTAND : STD_LOGIC; 
  signal registro6_M_1_FFY_RST : STD_LOGIC; 
  signal registro6_M_1_FFX_RST : STD_LOGIC; 
  signal registro6_M_3_FFY_RST : STD_LOGIC; 
  signal registro6_M_3_FFX_RST : STD_LOGIC; 
  signal registro1_M_3_FFX_RST : STD_LOGIC; 
  signal registro1_M_5_FFY_RST : STD_LOGIC; 
  signal registro1_M_5_FFX_RST : STD_LOGIC; 
  signal registro1_M_7_FFY_RST : STD_LOGIC; 
  signal registro1_M_7_FFX_RST : STD_LOGIC; 
  signal registro2_M_1_FFY_RST : STD_LOGIC; 
  signal registro2_M_1_FFX_RST : STD_LOGIC; 
  signal registro3_M_1_FFY_RST : STD_LOGIC; 
  signal registro3_M_1_FFX_RST : STD_LOGIC; 
  signal registro3_M_3_FFY_RST : STD_LOGIC; 
  signal registro3_M_3_FFX_RST : STD_LOGIC; 
  signal registro3_M_5_FFY_RST : STD_LOGIC; 
  signal registro3_M_5_FFX_RST : STD_LOGIC; 
  signal registro3_M_7_FFY_RST : STD_LOGIC; 
  signal registro3_M_7_FFX_RST : STD_LOGIC; 
  signal registro5_M_3_FFX_RST : STD_LOGIC; 
  signal registro5_M_5_FFY_RST : STD_LOGIC; 
  signal registro5_M_5_FFX_RST : STD_LOGIC; 
  signal registro5_M_7_FFY_RST : STD_LOGIC; 
  signal registro5_M_7_FFX_RST : STD_LOGIC; 
  signal count_aux_01_FFY_RST : STD_LOGIC; 
  signal count_aux_01_FFY_RSTAND : STD_LOGIC; 
  signal count_aux_0_2_FFY_RST : STD_LOGIC; 
  signal count_aux_0_2_FFY_RSTAND : STD_LOGIC; 
  signal count_aux_2_FFY_RST : STD_LOGIC; 
  signal count_aux_2_FFY_RSTAND : STD_LOGIC; 
  signal registro4_M_1_FFY_RST : STD_LOGIC; 
  signal registro4_M_1_FFX_RST : STD_LOGIC; 
  signal registro4_M_3_FFY_RST : STD_LOGIC; 
  signal registro4_M_3_FFX_RST : STD_LOGIC; 
  signal registro6_M_5_FFY_RST : STD_LOGIC; 
  signal registro6_M_5_FFX_RST : STD_LOGIC; 
  signal registro6_M_7_FFY_RST : STD_LOGIC; 
  signal registro6_M_7_FFX_RST : STD_LOGIC; 
  signal registro7_M_1_FFY_RST : STD_LOGIC; 
  signal registro7_M_1_FFX_RST : STD_LOGIC; 
  signal registro7_M_3_FFY_RST : STD_LOGIC; 
  signal registro7_M_3_FFX_RST : STD_LOGIC; 
  signal registro4_M_5_FFY_RST : STD_LOGIC; 
  signal registro4_M_5_FFX_RST : STD_LOGIC; 
  signal registro4_M_7_FFY_RST : STD_LOGIC; 
  signal registro4_M_7_FFX_RST : STD_LOGIC; 
  signal registro5_M_1_FFY_RST : STD_LOGIC; 
  signal registro5_M_1_FFX_RST : STD_LOGIC; 
  signal registro5_M_3_FFY_RST : STD_LOGIC; 
  signal registro7_M_5_FFY_RST : STD_LOGIC; 
  signal registro7_M_5_FFX_RST : STD_LOGIC; 
  signal registro1_M_1_FFY_RST : STD_LOGIC; 
  signal registro1_M_1_FFX_RST : STD_LOGIC; 
  signal registro7_M_7_FFY_RST : STD_LOGIC; 
  signal registro7_M_7_FFX_RST : STD_LOGIC; 
  signal registro1_M_3_FFY_RST : STD_LOGIC; 
  signal count_aux_0_FFY_RST : STD_LOGIC; 
  signal count_aux_0_FFX_RST : STD_LOGIC; 
  signal registro2_M_3_FFY_RST : STD_LOGIC; 
  signal registro2_M_3_FFX_RST : STD_LOGIC; 
  signal registro2_M_5_FFY_RST : STD_LOGIC; 
  signal registro2_M_5_FFX_RST : STD_LOGIC; 
  signal registro2_M_7_FFY_RST : STD_LOGIC; 
  signal registro2_M_7_FFX_RST : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal registro_salida_M : STD_LOGIC_VECTOR ( 19 downto 0 ); 
  signal sal_mult : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal count_aux : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal registro7_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal registro6_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal registro5_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal registro4_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal sal_mux : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal registro3_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal registro2_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal registro1_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal registro0_M : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal salida_rom : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal count_aux_n0000 : STD_LOGIC_VECTOR ( 2 downto 2 ); 
begin
  registro5_M_3_DXMUX_0 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro4_M(3),
      O => registro5_M_3_DXMUX
    );
  registro5_M_3_DYMUX_1 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro4_M(2),
      O => registro5_M_3_DYMUX
    );
  registro5_M_3_SRINV_2 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => registro5_M_3_SRINV
    );
  registro5_M_3_CLKINV_3 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => registro5_M_3_CLKINV
    );
  registro5_M_3_CEINV_4 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load_0,
      O => registro5_M_3_CEINV
    );
  registro5_M_5_DXMUX_5 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro4_M(5),
      O => registro5_M_5_DXMUX
    );
  registro5_M_5_DYMUX_6 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro4_M(4),
      O => registro5_M_5_DYMUX
    );
  registro5_M_5_SRINV_7 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => registro5_M_5_SRINV
    );
  registro5_M_5_CLKINV_8 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => registro5_M_5_CLKINV
    );
  registro5_M_5_CEINV_9 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load_0,
      O => registro5_M_5_CEINV
    );
  registro5_M_7_DXMUX_10 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro4_M(7),
      O => registro5_M_7_DXMUX
    );
  registro5_M_7_DYMUX_11 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => registro4_M(6),
      O => registro5_M_7_DYMUX
    );
  registro5_M_7_SRINV_12 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => reset_IBUF,
      O => registro5_M_7_SRINV
    );
  registro5_M_7_CLKINV_13 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => registro5_M_7_CLKINV
    );
  registro5_M_7_CEINV_14 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => load_0,
      O => registro5_M_7_CEINV
    );
  count_aux_01_DYMUX_15 : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => count_aux(0),
      O => count_aux_01_DYMUX
    );
  count_aux_01_CLKINV_16 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_aux_01_CLKINV
    );
  count_aux_0_2_DYMUX_17 : X_INV_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => count_aux(0),
      O => count_aux_0_2_DYMUX
    );
  count_aux_0_2_CLKINV_18 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => count_aux_0_2_CLKINV
    );
  count_aux_0_3_DYMUX_19 : X_INV_PP
    generic map(