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📄 filtro_fir_mac.twr

📁 This sources implement a 8-bit FIR Filter with selectable coefficent rom.
💻 TWR
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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:/Xilinx/ISE/bin/nt/trce.exe -ise
e:\mis documentos\teleco files\4 teleco\1er cuatrimestre\arquitectura de computadores [9][ac]\practicas\practica 2 filtro fir\filtro_fir.ise
-intstyle ise -e 3 -l 3 -s 4 -xml filtro_fir_mac filtro_fir_mac.ncd -o
filtro_fir_mac.twr filtro_fir_mac.pcf


Design file:              filtro_fir_mac.ncd
Physical constraint file: filtro_fir_mac.pcf
Device,speed:             xc3s400,-4 (PRODUCTION 1.35 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
enable      |    7.234(R)|   -0.074(R)|clk_BUFGP         |   0.000|
entrada<0>  |    2.851(R)|   -0.322(R)|clk_BUFGP         |   0.000|
entrada<1>  |    2.868(R)|   -0.342(R)|clk_BUFGP         |   0.000|
entrada<2>  |    2.868(R)|   -0.342(R)|clk_BUFGP         |   0.000|
entrada<3>  |    2.868(R)|   -0.342(R)|clk_BUFGP         |   0.000|
entrada<4>  |    2.868(R)|   -0.342(R)|clk_BUFGP         |   0.000|
entrada<5>  |    2.868(R)|   -0.342(R)|clk_BUFGP         |   0.000|
entrada<6>  |    2.868(R)|   -0.342(R)|clk_BUFGP         |   0.000|
entrada<7>  |    2.868(R)|   -0.342(R)|clk_BUFGP         |   0.000|
sel<0>      |   13.744(R)|   -4.045(R)|clk_BUFGP         |   0.000|
sel<1>      |   14.893(R)|   -4.359(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
salida<0>   |    7.363(R)|clk_BUFGP         |   0.000|
salida<10>  |    7.363(R)|clk_BUFGP         |   0.000|
salida<11>  |    7.363(R)|clk_BUFGP         |   0.000|
salida<12>  |    7.363(R)|clk_BUFGP         |   0.000|
salida<13>  |    7.363(R)|clk_BUFGP         |   0.000|
salida<14>  |    7.383(R)|clk_BUFGP         |   0.000|
salida<15>  |    7.383(R)|clk_BUFGP         |   0.000|
salida<16>  |    7.382(R)|clk_BUFGP         |   0.000|
salida<17>  |    7.363(R)|clk_BUFGP         |   0.000|
salida<18>  |    7.382(R)|clk_BUFGP         |   0.000|
salida<19>  |    7.382(R)|clk_BUFGP         |   0.000|
salida<1>   |    7.383(R)|clk_BUFGP         |   0.000|
salida<20>  |    7.363(R)|clk_BUFGP         |   0.000|
salida<21>  |    7.363(R)|clk_BUFGP         |   0.000|
salida<22>  |    7.383(R)|clk_BUFGP         |   0.000|
salida<2>   |    7.383(R)|clk_BUFGP         |   0.000|
salida<3>   |    7.363(R)|clk_BUFGP         |   0.000|
salida<4>   |    7.363(R)|clk_BUFGP         |   0.000|
salida<5>   |    7.382(R)|clk_BUFGP         |   0.000|
salida<6>   |    7.363(R)|clk_BUFGP         |   0.000|
salida<7>   |    7.382(R)|clk_BUFGP         |   0.000|
salida<8>   |    7.382(R)|clk_BUFGP         |   0.000|
salida<9>   |    7.382(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   15.833|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Wed Apr 22 01:23:50 2009
--------------------------------------------------------------------------------



Peak Memory Usage: 85 MB

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