send_cmd.v

SD card SDIO module send command and read response

module send_cmd (
	clk,
	reset_n,
	reset_s,
	go,
	done,
	in,
	cmd_oe,
//	shared resource
	byte_op_go,
	byte_op_done,
	byte_op_byte_in,
	byte_op_send_receive,

	calc_crc_go,
	calc_crc_done,
	calc_crc_byte_in,
	calc_crc_in,
	calc_crc_out
	);
	
input  clk;
input  reset_n;
input  reset_s;
input  go;
output done;
input  [47:0] in;
output cmd_oe;
output byte_op_go;
input  byte_op_done;
output [7:0] byte_op_byte_in;
output byte_op_send_receive;
output calc_crc_go;
input  calc_crc_done;
output [7:0] calc_crc_byte_in;
output [7:0] calc_crc_in;
input  [7:0] calc_crc_out;

parameter
	ST_IDLE		= 8'h00,
	ST_INIT		= 8'h01,
	ST_NCC_WRET	= 8'h02,
	ST_LP1_IC	= 8'h03,
	ST_LP1_E		= 8'h04,
	ST_LP1_WRET	= 8'h05,
	ST_LP3_E		= 8'h06,
	ST_LP3_WRET	= 8'h07,
	ST_DONE		= 8'h08;

reg [7:0] state;
wire [7:0] next;

always @(posedge clk or negedge rst_n)
	if (!reset_n || reset_s) state <= ST_IDLE;
	else state <= next;

always @(state or go or i or byte_op_done or calc_crc_done)
	begin
	next = 'bx;
	case (state)
		ST_IDLE		: 	if (go)	next = ST_INIT;
							else 		next = ST_IDLE;

		ST_INIT		:				next = ST_NCC_WRET;
// ncc
		ST_NCC_WRET	:	if (byte_op_done) next = ST_LP1_E;
							else		next = ST_NCC_WRET;
// send CMD
		ST_LP1_IC	:	if (i<8'h05) next = ST_LP1_E;
							else 		next = ST_LP3_E;

		ST_LP1_E		: 				next = ST_LP1_WRET;

		ST_LP1_WRET	:	if (byte_op_done && calc_crc_done)
										next = ST_LP1_IC;
							else		next = ST_LP1_WRET;

// send CRC
		ST_LP3_E		: 				next = ST_LP3_WRET;

		ST_LP3_WRET	:	if (byte_op_done)
										next = ST_DONE;
							else		next = ST_LP3_WRET;

// DONE
		ST_DONE  	: 	if (!go) next = ST_IDLE;
							else  	next = ST_INIT;
	endcase
	end

assign byte_op_go = (next == ST_INIT || next == ST_LP1_E || next == ST_LP3_E);
assign byte_op_send_receive = 1'b1; // send

assign calc_crc_go = byte_op_go;
assign calc_crc_byte_in = byte_op_byte_in;
assign calc_crc_in = crc;

always @(next or i or crc)
	begin
	if (next == ST_LP1_E)
		case (i)
			0	:	byte_op_byte_in = in[47:40];
			1	:	byte_op_byte_in = in[39:32];
			2	:	byte_op_byte_in = in[31:24];
			3	:	byte_op_byte_in = in[23:16];
			4	:	byte_op_byte_in = in[15:8];
			default : byte_op_byte_in = 8'h00;
		endcase
	else if (next == ST_LP3_E)
		byte_op_byte_in = ((crc << 1) | 8'h01);
	end

reg cmd_oe_r;
assign cmd_oe = cmd_oe_r;
	
always @(posedge clk or negedge rst_n)
	if (!reset_n || reset_s)
	begin
		i <= 8'h00;
		crc <= 8'h00;
		done_r <= 1'b1;
		cmd_oe_r <= 1'b0;
	end	else
	case (next)
		ST_IDLE		:;
// send CMD
		ST_INIT		:	begin
							crc <= 8'h00;
							cmd_oe_r <= 1'b0;
							done_r <= 1'b0;
							i <= 8'h00;
							end;
		ST_LP3_E		:	cmd_oe_r <= 1'b1;
		ST_LP1_IC	:	begin
							i <= i + 8'h01;
							crc <= calc_crc_out;
							end
// send CRC
// DONE
		ST_DONE  	:	done_r <= 1'b1;
	endcase

assign done = done_r && !go;

endmodule