wait_data.v

来自「module to wait data on DAT line SDIO mod」· Verilog 代码 · 共 80 行

module wait_data(
		clk,
		reset_n,
		reset_s,
		go,
		done,
		err,
		sd_dat_cmd_in,
		sd_clk_rising_edge,
		sd_clk_hold,
	);

input clk;
input reset_n;
input reset_s;
input go;
output done;
output err;
output sd_clk_hold;
input sd_dat_cmd_in;
input sd_clk_rising_edge;

parameter
	ST_IDLE		= 8'h00,
	ST_INIT		= 8'h01,
	ST_WAIT		= 8'h02,
	ST_DONE		= 8'h03;

parameter MAX_WAIT = 8'h64;
	
reg [7:0] state, next;
reg [7:0] cnt_r;
reg done_r;
reg sd_dat_cmd_in_r;

always @(posedge clk or negedge reset_n)
	if (!reset_n || reset_s) state <= ST_IDLE;
	else state <= next;
	
always @(state or go or sd_dat_cmd_in or cnt_r or sd_dat_cmd_in_r)
	begin
	next = 'bx;
	case (state)
		ST_IDLE	:	if (go) 	next = ST_INIT;
							else  next = ST_IDLE;
		ST_INIT	:	next = ST_WAIT;
		ST_WAIT	:	if (!sd_dat_cmd_in_r || (cnt_r > MAX_WAIT))
									next = ST_DONE;
						else		next = ST_WAIT;

		ST_DONE  : 	if (!go) next = ST_IDLE;
							else  next = ST_INIT;
	endcase
	end
assign sd_clk_hold = (next != ST_WAIT);
always @(posedge clk or negedge reset_n)
	if (!reset_n || reset_s)
	begin
		done_r <= 1'b1;
		cnt_r  <= 8'h00;
	end	else
	case (next)
		ST_INIT	:	begin
					done_r <= 1'b0;
					cnt_r  <= 8'h00;
					sd_dat_cmd_in_r <= 1'b1;
					end
		ST_WAIT	:	if (sd_clk_rising_edge)
						begin
						cnt_r  <= cnt_r + 8'h01;
						sd_dat_cmd_in_r <= sd_dat_cmd_in;
						end
		ST_DONE  :	done_r <= 1'b1;
	endcase

assign done = done_r && !go;
assign err  = (cnt_r >= MAX_WAIT);
endmodule