texi.tan.qmsg

在Quartus II 5.0环境下

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "fee4\[1\] temp2\[3\] clk 547 ps " "Info: Found hold time violation between source  pin or register \"fee4\[1\]\" and destination pin or register \"temp2\[3\]\" for clock \"clk\" (Hold time is 547 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.447 ns + Largest " "Info: + Largest clock skew is 4.447 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.569 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.569 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "" { clk } "NODE_NAME" } "" } } { "texi.v" "" { Text "C:/altera/0412/texi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clkbase 2 REG LC_X15_Y10_N8 59 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X15_Y10_N8; Fanout = 59; REG Node = 'clkbase'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "1.680 ns" { clk clkbase } "NODE_NAME" } "" } } { "texi.v" "" { Text "C:/altera/0412/texi.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.232 ns) + CELL(0.935 ns) 8.316 ns speed 3 REG LC_X8_Y10_N5 59 " "Info: 3: + IC(4.232 ns) + CELL(0.935 ns) = 8.316 ns; Loc. = LC_X8_Y10_N5; Fanout = 59; REG Node = 'speed'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "5.167 ns" { clkbase speed } "NODE_NAME" } "" } } { "texi.v" "" { Text "C:/altera/0412/texi.v" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.542 ns) + CELL(0.711 ns) 12.569 ns temp2\[3\] 4 REG LC_X16_Y13_N6 3 " "Info: 4: + IC(3.542 ns) + CELL(0.711 ns) = 12.569 ns; Loc. = LC_X16_Y13_N6; Fanout = 3; REG Node = 'temp2\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "4.253 ns" { speed temp2[3] } "NODE_NAME" } "" } } { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 32.22 % ) " "Info: Total cell delay = 4.050 ns ( 32.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.519 ns ( 67.78 % ) " "Info: Total interconnect delay = 8.519 ns ( 67.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "12.569 ns" { clk clkbase speed temp2[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.569 ns" { clk clk~out0 clkbase speed temp2[3] } { 0.000ns 0.000ns 0.745ns 4.232ns 3.542ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.122 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 8.122 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_152 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 26; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "" { clk } "NODE_NAME" } "" } } { "texi.v" "" { Text "C:/altera/0412/texi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns clkbase 2 REG LC_X15_Y10_N8 59 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X15_Y10_N8; Fanout = 59; REG Node = 'clkbase'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "1.680 ns" { clk clkbase } "NODE_NAME" } "" } } { "texi.v" "" { Text "C:/altera/0412/texi.v" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.262 ns) + CELL(0.711 ns) 8.122 ns fee4\[1\] 3 REG LC_X16_Y14_N3 1 " "Info: 3: + IC(4.262 ns) + CELL(0.711 ns) = 8.122 ns; Loc. = LC_X16_Y14_N3; Fanout = 1; REG Node = 'fee4\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "4.973 ns" { clkbase fee4[1] } "NODE_NAME" } "" } } { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.35 % ) " "Info: Total cell delay = 3.115 ns ( 38.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.007 ns ( 61.65 % ) " "Info: Total interconnect delay = 5.007 ns ( 61.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "8.122 ns" { clk clkbase fee4[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.122 ns" { clk clk~out0 clkbase fee4[1] } { 0.000ns 0.000ns 0.745ns 4.262ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "12.569 ns" { clk clkbase speed temp2[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.569 ns" { clk clk~out0 clkbase speed temp2[3] } { 0.000ns 0.000ns 0.745ns 4.232ns 3.542ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "8.122 ns" { clk clkbase fee4[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.122 ns" { clk clk~out0 clkbase fee4[1] } { 0.000ns 0.000ns 0.745ns 4.262ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.691 ns - Shortest register register " "Info: - Shortest register to register delay is 3.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fee4\[1\] 1 REG LC_X16_Y14_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y14_N3; Fanout = 1; REG Node = 'fee4\[1\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "" { fee4[1] } "NODE_NAME" } "" } } { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.524 ns) + CELL(0.114 ns) 0.638 ns temp2\[4\]~125 2 COMB LC_X16_Y14_N8 1 " "Info: 2: + IC(0.524 ns) + CELL(0.114 ns) = 0.638 ns; Loc. = LC_X16_Y14_N8; Fanout = 1; COMB Node = 'temp2\[4\]~125'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "0.638 ns" { fee4[1] temp2[4]~125 } "NODE_NAME" } "" } } { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.453 ns) + CELL(0.292 ns) 1.383 ns temp2\[4\]~129 3 COMB LC_X16_Y14_N0 5 " "Info: 3: + IC(0.453 ns) + CELL(0.292 ns) = 1.383 ns; Loc. = LC_X16_Y14_N0; Fanout = 5; COMB Node = 'temp2\[4\]~129'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "0.745 ns" { temp2[4]~125 temp2[4]~129 } "NODE_NAME" } "" } } { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.441 ns) + CELL(0.867 ns) 3.691 ns temp2\[3\] 4 REG LC_X16_Y13_N6 3 " "Info: 4: + IC(1.441 ns) + CELL(0.867 ns) = 3.691 ns; Loc. = LC_X16_Y13_N6; Fanout = 3; REG Node = 'temp2\[3\]'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "2.308 ns" { temp2[4]~129 temp2[3] } "NODE_NAME" } "" } } { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.273 ns ( 34.49 % ) " "Info: Total cell delay = 1.273 ns ( 34.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.418 ns ( 65.51 % ) " "Info: Total interconnect delay = 2.418 ns ( 65.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "3.691 ns" { fee4[1] temp2[4]~125 temp2[4]~129 temp2[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.691 ns" { fee4[1] temp2[4]~125 temp2[4]~129 temp2[3] } { 0.000ns 0.524ns 0.453ns 1.441ns } { 0.000ns 0.114ns 0.292ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "12.569 ns" { clk clkbase speed temp2[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.569 ns" { clk clk~out0 clkbase speed temp2[3] } { 0.000ns 0.000ns 0.745ns 4.232ns 3.542ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "8.122 ns" { clk clkbase fee4[1] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "8.122 ns" { clk clk~out0 clkbase fee4[1] } { 0.000ns 0.000ns 0.745ns 4.262ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "3.691 ns" { fee4[1] temp2[4]~125 temp2[4]~129 temp2[3] } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.691 ns" { fee4[1] temp2[4]~125 temp2[4]~129 temp2[3] } { 0.000ns 0.524ns 0.453ns 1.441ns } { 0.000ns 0.114ns 0.292ns 0.867ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "deout\[5\]~reg0 waitselect clk 16.788 ns register " "Info: tsu for register \"deout\[5\]~reg0\" (data pin = \"waitselect\", clock pin = \"clk\") is 16.788 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.713 ns + Longest pin register " "Info: + Longest pin to register delay is 19.713 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns waitselect 1 PIN PIN_18 55 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_18; Fanout = 55; PIN Node = 'waitselect'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "texi" "UNKNOWN" "V1" "C:/altera/0412/db/texi.quartus_db" { Floorplan "C:/altera/0412/" "" "" { waitselect } "NODE_NAME" } "" } } { "texi.v" "" { Text "C:/altera/0412/texi.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s!