texi.tan.qmsg

在Quartus II 5.0环境下

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "begincost\[1\] " "Warning: Node \"begincost\[1\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepk\[4\] " "Warning: Node \"feepk\[4\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepk\[3\] " "Warning: Node \"feepk\[3\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepk\[2\] " "Warning: Node \"feepk\[2\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepk\[1\] " "Warning: Node \"feepk\[1\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "addlicheng\[1\] " "Warning: Node \"addlicheng\[1\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "addlicheng\[3\] " "Warning: Node \"addlicheng\[3\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "addlicheng\[2\] " "Warning: Node \"addlicheng\[2\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepk\[6\] " "Warning: Node \"feepk\[6\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepksave22\[1\] " "Warning: Node \"feepksave22\[1\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepk\[5\] " "Warning: Node \"feepk\[5\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepk\[7\] " "Warning: Node \"feepk\[7\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepk\[8\] " "Warning: Node \"feepk\[8\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "begincost\[4\] " "Warning: Node \"begincost\[4\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "begincost\[2\] " "Warning: Node \"begincost\[2\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "begincost\[3\] " "Warning: Node \"begincost\[3\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepksave11\[2\] " "Warning: Node \"feepksave11\[2\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepksave11\[1\] " "Warning: Node \"feepksave11\[1\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepksave11\[3\] " "Warning: Node \"feepksave11\[3\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepksave11\[4\] " "Warning: Node \"feepksave11\[4\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepksave22\[2\] " "Warning: Node \"feepksave22\[2\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepksave22\[4\] " "Warning: Node \"feepksave22\[4\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTAN_COMB_LATCH_NODE" "feepksave22\[3\] " "Warning: Node \"feepksave22\[3\]\" is a latch" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 2 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "en " "Info: Assuming node \"en\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 2 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "clr " "Info: Assuming node \"clr\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 2 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "enset\[2\] " "Info: Assuming node \"enset\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "enset\[1\] " "Info: Assuming node \"enset\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "always1~3 " "Info: Detected gated clock \"always1~3\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "always1~3" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "always1~1 " "Info: Detected gated clock \"always1~1\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "always1~1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "always1~14 " "Info: Detected gated clock \"always1~14\" as buffer" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "always1~14" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "speed " "Info: Detected ripple clock \"speed\" as buffer" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 56 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "speed" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clktime " "Info: Detected ripple clock \"clktime\" as buffer" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 58 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clktime" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clkbase " "Info: Detected ripple clock \"clkbase\" as buffer" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 55 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clkbase" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}