texi.map.qmsg

在Quartus II 5.0环境下

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "temp data_in GND " "Warning: Reduced register \"temp\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 64 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fee4\[5\] data_in GND " "Warning: Reduced register \"fee4\[5\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "speedcount\[8\] data_in GND " "Warning: Reduced register \"speedcount\[8\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 80 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "speedcount\[7\] data_in GND " "Warning: Reduced register \"speedcount\[7\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 80 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "speedcount\[6\] data_in GND " "Warning: Reduced register \"speedcount\[6\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 80 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "speedcount\[5\] data_in GND " "Warning: Reduced register \"speedcount\[5\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 80 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "temp5\[3\] data_in GND " "Warning: Reduced register \"temp5\[3\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "displaycount\[11\] data_in GND " "Warning: Reduced register \"displaycount\[11\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 308 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "displaycount\[10\] data_in GND " "Warning: Reduced register \"displaycount\[10\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 308 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "displaycount\[9\] data_in GND " "Warning: Reduced register \"displaycount\[9\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 308 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "speedcount\[4\] data_in GND " "Warning: Reduced register \"speedcount\[4\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 80 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "speedcount\[3\] data_in GND " "Warning: Reduced register \"speedcount\[3\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 80 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addlicheng\[1\] " "Warning: Latch addlicheng\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[1\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addlicheng\[2\] " "Warning: Latch addlicheng\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[1\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "addlicheng\[3\] " "Warning: Latch addlicheng\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[1\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "begincost\[4\] " "Warning: Latch begincost\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[2\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "begincost\[3\] " "Warning: Latch begincost\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[2\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "begincost\[2\] " "Warning: Latch begincost\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[2\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "begincost\[1\] " "Warning: Latch begincost\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[2\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "feepk\[4\] " "Warning: Latch feepk\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[1\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "feepk\[2\] " "Warning: Latch feepk\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[1\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "feepk\[3\] " "Warning: Latch feepk\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[1\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "feepk\[1\] " "Warning: Latch feepk\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[1\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "feepk\[8\] " "Warning: Latch feepk\[8\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[1\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "feepk\[6\] " "Warning: Latch feepk\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[1\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "feepk\[7\] " "Warning: Latch feepk\[7\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[1\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "feepk\[5\] " "Warning: Latch feepk\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA enset\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal enset\[1\]" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 4 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 87 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "displaycount\[6\] data_in GND " "Warning: Reduced register \"displaycount\[6\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 308 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "displaycount\[7\] data_in GND " "Warning: Reduced register \"displaycount\[7\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 308 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "displaycount\[8\] data_in GND " "Warning: Reduced register \"displaycount\[8\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 308 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "set " "Warning: No output dependent on input pin \"set\"" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 2 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "625 " "Info: Implemented 625 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "593 " "Info: Implemented 593 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 113 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 113 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 18 23:55:37 2007 " "Info: Processing ended: Thu Oct 18 23:55:37 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}