texi.map.qmsg

来自「在Quartus II 5.0环境下」· QMSG 代码 · 共 106 行 · 第 1/3 页

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 texi.v(354) " "Warning (10230): Verilog HDL assignment warning at texi.v(354): truncated value with size 32 to match size of target (4)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 354 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(361) " "Warning (10230): Verilog HDL assignment warning at texi.v(361): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 361 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(363) " "Warning (10230): Verilog HDL assignment warning at texi.v(363): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 363 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(364) " "Warning (10230): Verilog HDL assignment warning at texi.v(364): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 364 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 texi.v(376) " "Warning (10230): Verilog HDL assignment warning at texi.v(376): truncated value with size 32 to match size of target (4)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 376 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(388) " "Warning (10230): Verilog HDL assignment warning at texi.v(388): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 388 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(389) " "Warning (10230): Verilog HDL assignment warning at texi.v(389): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 389 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(393) " "Warning (10230): Verilog HDL assignment warning at texi.v(393): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 393 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "feepksave22 texi.v(311) " "Warning (10240): Verilog HDL Always Construct warning at texi.v(311): variable \"feepksave22\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"feepksave22\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 311 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "feepksave11 texi.v(311) " "Warning (10240): Verilog HDL Always Construct warning at texi.v(311): variable \"feepksave11\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"feepksave11\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 311 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 texi.v(420) " "Warning (10230): Verilog HDL assignment warning at texi.v(420): truncated value with size 32 to match size of target (6)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 420 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 texi.v(421) " "Warning (10230): Verilog HDL assignment warning at texi.v(421): truncated value with size 32 to match size of target (9)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 421 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 texi.v(422) " "Warning (10230): Verilog HDL assignment warning at texi.v(422): truncated value with size 32 to match size of target (4)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 422 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(423) " "Warning (10230): Verilog HDL assignment warning at texi.v(423): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 423 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 texi.v(428) " "Warning (10230): Verilog HDL assignment warning at texi.v(428): truncated value with size 32 to match size of target (4)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 428 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(429) " "Warning (10230): Verilog HDL assignment warning at texi.v(429): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 429 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 texi.v(434) " "Warning (10230): Verilog HDL assignment warning at texi.v(434): truncated value with size 32 to match size of target (4)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 434 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 texi.v(435) " "Warning (10230): Verilog HDL assignment warning at texi.v(435): truncated value with size 32 to match size of target (4)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 435 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(438) " "Warning (10230): Verilog HDL assignment warning at texi.v(438): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 438 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(439) " "Warning (10230): Verilog HDL assignment warning at texi.v(439): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 439 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(440) " "Warning (10230): Verilog HDL assignment warning at texi.v(440): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 440 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fee21\[5\] data_in GND " "Warning: Reduced register \"fee21\[5\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 404 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fee21\[4\] data_in GND " "Warning: Reduced register \"fee21\[4\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 404 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fee21\[3\] data_in GND " "Warning: Reduced register \"fee21\[3\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 404 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fee21\[2\] data_in GND " "Warning: Reduced register \"fee21\[2\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 404 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fee21\[1\] data_in GND " "Warning: Reduced register \"fee21\[1\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 404 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "displaystate\[4\] data_in GND " "Warning: Reduced register \"displaystate\[4\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 308 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "displaycount\[15\] data_in GND " "Warning: Reduced register \"displaycount\[15\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 308 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "displaycount\[14\] data_in GND " "Warning: Reduced register \"displaycount\[14\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 308 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "displaycount\[13\] data_in GND " "Warning: Reduced register \"displaycount\[13\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 308 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "displaycount\[12\] data_in GND " "Warning: Reduced register \"displaycount\[12\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 308 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fee24\[5\] data_in GND " "Warning: Reduced register \"fee24\[5\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 404 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fee14\[5\] data_in GND " "Warning: Reduced register \"fee14\[5\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 313 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clktimecount\[8\] data_in GND " "Warning: Reduced register \"clktimecount\[8\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 80 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clktimecount\[7\] data_in GND " "Warning: Reduced register \"clktimecount\[7\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 80 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "clktimecount\[6\] data_in GND " "Warning: Reduced register \"clktimecount\[6\]\" with stuck data_in port to stuck value GND" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 80 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}