texi.map.qmsg

在Quartus II 5.0环境下

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 18 23:55:26 2007 " "Info: Processing started: Thu Oct 18 23:55:26 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off texi -c texi " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off texi -c texi" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "texi.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file texi.v" { { "Info" "ISGN_ENTITY_NAME" "1 texi " "Info: Found entity 1: texi" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "texi " "Info: Elaborating entity \"texi\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "set texi.v(2) " "Info (10035): Verilog HDL or VHDL information at texi.v(2): object \"set\" declared but not used" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 2 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 texi.v(73) " "Warning (10230): Verilog HDL assignment warning at texi.v(73): truncated value with size 32 to match size of target (8)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 texi.v(77) " "Warning (10230): Verilog HDL assignment warning at texi.v(77): truncated value with size 32 to match size of target (8)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(113) " "Warning (10230): Verilog HDL assignment warning at texi.v(113): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 113 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(114) " "Warning (10230): Verilog HDL assignment warning at texi.v(114): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 114 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(118) " "Warning (10230): Verilog HDL assignment warning at texi.v(118): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 118 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(119) " "Warning (10230): Verilog HDL assignment warning at texi.v(119): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 119 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(123) " "Warning (10230): Verilog HDL assignment warning at texi.v(123): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 123 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 texi.v(129) " "Warning (10230): Verilog HDL assignment warning at texi.v(129): truncated value with size 32 to match size of target (12)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 129 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 texi.v(130) " "Warning (10230): Verilog HDL assignment warning at texi.v(130): truncated value with size 32 to match size of target (3)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 130 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "texi.v(137) " "Warning (10270): Verilog HDL statement warning at texi.v(137): incomplete Case Statement has no default case item" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 137 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "begincost texi.v(85) " "Warning (10240): Verilog HDL Always Construct warning at texi.v(85): variable \"begincost\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"begincost\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 85 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "feepk texi.v(85) " "Warning (10240): Verilog HDL Always Construct warning at texi.v(85): variable \"feepk\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"feepk\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 85 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "addlicheng texi.v(85) " "Warning (10240): Verilog HDL Always Construct warning at texi.v(85): variable \"addlicheng\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"addlicheng\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 85 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 15 texi.v(190) " "Warning (10230): Verilog HDL assignment warning at texi.v(190): truncated value with size 32 to match size of target (15)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 190 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 texi.v(191) " "Warning (10230): Verilog HDL assignment warning at texi.v(191): truncated value with size 32 to match size of target (4)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 191 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "texi.v(198) " "Warning (10270): Verilog HDL statement warning at texi.v(198): incomplete Case Statement has no default case item" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 198 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "texi.v(215) " "Warning (10270): Verilog HDL statement warning at texi.v(215): incomplete Case Statement has no default case item" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 215 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "texi.v(226) " "Warning (10270): Verilog HDL statement warning at texi.v(226): incomplete Case Statement has no default case item" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 226 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "texi.v(235) " "Warning (10270): Verilog HDL statement warning at texi.v(235): incomplete Case Statement has no default case item" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 235 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "texi.v(249) " "Warning (10270): Verilog HDL statement warning at texi.v(249): incomplete Case Statement has no default case item" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 249 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "texi.v(257) " "Warning (10270): Verilog HDL statement warning at texi.v(257): incomplete Case Statement has no default case item" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 257 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "texi.v(272) " "Warning (10270): Verilog HDL statement warning at texi.v(272): incomplete Case Statement has no default case item" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 272 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(320) " "Warning (10230): Verilog HDL assignment warning at texi.v(320): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 320 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(331) " "Warning (10230): Verilog HDL assignment warning at texi.v(331): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 331 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(334) " "Warning (10230): Verilog HDL assignment warning at texi.v(334): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 334 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 texi.v(335) " "Warning (10230): Verilog HDL assignment warning at texi.v(335): truncated value with size 32 to match size of target (5)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 335 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 texi.v(347) " "Warning (10230): Verilog HDL assignment warning at texi.v(347): truncated value with size 32 to match size of target (9)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 347 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 texi.v(350) " "Warning (10230): Verilog HDL assignment warning at texi.v(350): truncated value with size 32 to match size of target (4)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 350 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 texi.v(352) " "Warning (10230): Verilog HDL assignment warning at texi.v(352): truncated value with size 32 to match size of target (4)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 352 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 texi.v(353) " "Warning (10230): Verilog HDL assignment warning at texi.v(353): truncated value with size 32 to match size of target (4)" {  } { { "texi.v" "" { Text "C:/altera/0412/texi.v" 353 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}