📄 texi_vhd.sdo
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// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP1C6Q240C8 Package PQFP240
//
//
// This SDF file should be used for PrimeTime (VHDL) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "texi")
(DATE "10/18/2007 23:55:20")
(VENDOR "Altera")
(PROGRAM "Quartus II")
(VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\clktime\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datac (619:619:619) (619:619:619))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\clktime\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT datain (734:734:734) (734:734:734))
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (4943:4943:4943) (4943:4943:4943))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\speed\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datac (565:565:565) (565:565:565))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\speed\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT datain (680:680:680) (680:680:680))
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (4943:4943:4943) (4943:4943:4943))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\clktimecount\[5\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (616:616:616) (616:616:616))
(PORT datab (528:528:528) (528:528:528))
(PORT datac (578:578:578) (578:578:578))
(PORT datad (429:429:429) (429:429:429))
(IOPATH dataa regin (738:738:738) (738:738:738))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH datad regin (309:309:309) (309:309:309))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\clktimecount\[5\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1056:1056:1056) (1056:1056:1056))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\clktimecount\[5\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (4943:4943:4943) (4943:4943:4943))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\speedcount\[2\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (514:514:514) (514:514:514))
(PORT datac (560:560:560) (560:560:560))
(IOPATH datab regin (607:607:607) (607:607:607))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\speedcount\[2\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1038:1038:1038) (1038:1038:1038))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\speedcount\[2\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (4943:4943:4943) (4943:4943:4943))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\clktimecount\[4\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (618:618:618) (618:618:618))
(PORT datab (530:530:530) (530:530:530))
(PORT datac (578:578:578) (578:578:578))
(PORT datad (430:430:430) (430:430:430))
(IOPATH dataa regin (738:738:738) (738:738:738))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH datad regin (309:309:309) (309:309:309))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\clktimecount\[4\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1056:1056:1056) (1056:1056:1056))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\clktimecount\[4\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (4943:4943:4943) (4943:4943:4943))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\clktimecount\[3\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (599:599:599) (599:599:599))
(PORT datab (536:536:536) (536:536:536))
(PORT datac (621:621:621) (621:621:621))
(PORT datad (549:549:549) (549:549:549))
(IOPATH dataa regin (738:738:738) (738:738:738))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH datad regin (309:309:309) (309:309:309))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\clktimecount\[3\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1099:1099:1099) (1099:1099:1099))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\clktimecount\[3\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (4943:4943:4943) (4943:4943:4943))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\clktimecount\[1\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (596:596:596) (596:596:596))
(PORT datac (621:621:621) (621:621:621))
(IOPATH dataa regin (738:738:738) (738:738:738))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\clktimecount\[1\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1099:1099:1099) (1099:1099:1099))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\clktimecount\[1\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (4943:4943:4943) (4943:4943:4943))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\clktimecount\[2\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (605:605:605) (605:605:605))
(PORT datac (615:615:615) (615:615:615))
(PORT datad (544:544:544) (544:544:544))
(IOPATH dataa regin (738:738:738) (738:738:738))
(IOPATH datad regin (309:309:309) (309:309:309))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\clktimecount\[2\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1093:1093:1093) (1093:1093:1093))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\clktimecount\[2\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (4943:4943:4943) (4943:4943:4943))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\add\~9737_I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datac (611:611:611) (611:611:611))
(PORT datad (545:545:545) (545:545:545))
(IOPATH datac combout (292:292:292) (292:292:292))
(IOPATH datad combout (114:114:114) (114:114:114))
)
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\speedcount\[1\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT datab (513:513:513) (513:513:513))
(PORT datac (562:562:562) (562:562:562))
(IOPATH datab regin (607:607:607) (607:607:607))
)
)
)
(CELL
(CELLTYPE "AND2")
(INSTANCE \\speedcount\[1\]\~I\\.regin_datac)
(DELAY
(ABSOLUTE
(PORT IN2 (1040:1040:1040) (1040:1040:1040))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\speedcount\[1\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (4943:4943:4943) (4943:4943:4943))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
(CELL
(CELLTYPE "cyclone_asynch_io")
(INSTANCE \\clk\~I\\.asynch_inst)
(DELAY
(ABSOLUTE
(IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
)
)
)
(CELL
(CELLTYPE "cyclone_asynch_io")
(INSTANCE \\en\~I\\.asynch_inst)
(DELAY
(ABSOLUTE
(IOPATH padio combout (1469:1469:1469) (1469:1469:1469))
)
)
)
(CELL
(CELLTYPE "cyclone_asynch_lcell")
(INSTANCE \\displaycount\[3\]\~I\\.lecomb)
(DELAY
(ABSOLUTE
(PORT dataa (468:468:468) (468:468:468))
(PORT datab (452:452:452) (452:452:452))
(PORT datad (504:504:504) (504:504:504))
(IOPATH dataa regin (738:738:738) (738:738:738))
(IOPATH datab regin (607:607:607) (607:607:607))
(IOPATH datad regin (309:309:309) (309:309:309))
)
)
)
(CELL
(CELLTYPE "cyclone_lcell_register")
(INSTANCE \\displaycount\[3\]\~I\\.lereg)
(DELAY
(ABSOLUTE
(PORT aclr (898:898:898) (898:898:898))
(PORT clk (1456:1456:1456) (1456:1456:1456))
(IOPATH (posedge clk) regout (224:224:224) (224:224:224))
(IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
)
)
(TIMINGCHECK
(SETUP datain (posedge clk) (37:37:37))
(HOLD datain (posedge clk) (15:15:15))
)
)
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