texi.vho

在Quartus II 5.0环境下

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

-- DATE "10/18/2007 23:55:20"

-- 
-- Device: Altera EP1C6Q240C8 Package PQFP240
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	texi IS
    PORT (
	clr : IN std_logic;
	start : IN std_logic;
	set : IN std_logic;
	setall : IN std_logic_vector(8 DOWNTO 1);
	enset : IN std_logic_vector(2 DOWNTO 1);
	en : IN std_logic;
	clk : IN std_logic;
	waitselect : IN std_logic;
	displayselect : IN std_logic;
	deout : OUT std_logic_vector(7 DOWNTO 1);
	flag : OUT std_logic_vector(2 DOWNTO 1);
	control : OUT std_logic_vector(5 DOWNTO 1);
	dot : OUT std_logic
	);
END texi;

ARCHITECTURE structure OF texi IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_clr : std_logic;
SIGNAL ww_start : std_logic;
SIGNAL ww_set : std_logic;
SIGNAL ww_setall : std_logic_vector(8 DOWNTO 1);
SIGNAL ww_enset : std_logic_vector(2 DOWNTO 1);
SIGNAL ww_en : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_waitselect : std_logic;
SIGNAL ww_displayselect : std_logic;
SIGNAL ww_deout : std_logic_vector(7 DOWNTO 1);
SIGNAL ww_flag : std_logic_vector(2 DOWNTO 1);
SIGNAL ww_control : std_logic_vector(5 DOWNTO 1);
SIGNAL ww_dot : std_logic;
SIGNAL \clktime~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clktime~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \speed~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \speed~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clktimecount[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clktimecount[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \speedcount[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \speedcount[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clktimecount[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clktimecount[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clktimecount[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clktimecount[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clktimecount[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clktimecount[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clktimecount[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \clktimecount[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9737_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9737_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \speedcount[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \speedcount[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clk~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \en~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \displaycount[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \displaycount[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9555_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9555_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \displaycount[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \displaycount[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9382_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9382_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \displaycount[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \displaycount[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9142_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9142_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9147_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9147_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \displaycount[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \displaycount[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9152_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9152_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \displaycount[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \displaycount[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9157_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9157_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \LessThan~2744_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \LessThan~2744_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \displaystate[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \displaystate[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \displaystate[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \displaystate[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \displaystate[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \displaystate[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \control[4]~4303_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \control[4]~4303_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \start~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \deout1~2579_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \deout1~2579_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \waitselect~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \deout1~2580_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \deout1~2580_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \clr~I_modesel\ : std_logic_vector(26 DOWNTO 0);
SIGNAL \control[4]~4305_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \control[4]~4305_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \timecount3[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \timecount3[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9468_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9468_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \timecount3[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \timecount3[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9473_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9473_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \timecount3[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \timecount3[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9463_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9463_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9478_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9478_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \timecount3[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \timecount3[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9483_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9483_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \timecount3[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \timecount3[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9488_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9488_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \timecount3[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \timecount3[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9493_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9493_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \timecount3[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \timecount3[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9498_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9498_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~1134_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~1134_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \timecount3[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \timecount3[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~1133_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~1133_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \timecount3[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \timecount3[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9458_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9458_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \licheng1[1]~243_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \licheng1[1]~243_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \licheng4[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \licheng4[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \licheng1[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \licheng1[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \licheng1[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \licheng1[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9591_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9591_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9596_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9596_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \licheng1[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \licheng1[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9595_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9595_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \licheng1[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \licheng1[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \LessThan~2756_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \LessThan~2756_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \licheng2[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \licheng2[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \licheng2[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \licheng2[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \licheng2[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \licheng2[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~3_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~3_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9549_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9549_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \licheng2~113_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \licheng2~113_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~1130_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~1130_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \licheng2[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \licheng2[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9451_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \add~9451_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \licheng3[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \licheng3[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \add~9452_I_modesel\ : std_logic_vector(12 DOWNTO 0);