texi.v

在Quartus II 5.0环境下

module texi(clr,start,set,setall,enset,en,clk,waitselect,displayselect,deout,flag,control,dot);
input clr,start,set,en,clk,waitselect,displayselect;
input [8:1]setall;
input [2:1]enset;
output dot;
output [7:1]deout;
output [2:1]flag;
output [5:1]control;

reg dot;
reg [7:1]deout;
reg [20:1]display;
reg [2:1]flag;

reg [4:1]licheng1;
reg [4:1]licheng2;
reg [4:1]licheng3;
reg [4:1]licheng4;

reg [5:1]fee1;
reg [5:1]fee2;
reg [5:1]fee3;
reg [5:1]fee4;


reg [5:1]fee11;
reg [5:1]fee12;
reg [5:1]fee13;
reg [5:1]fee14;

reg [5:1]fee21;
reg [5:1]fee22;
reg [5:1]fee23;
reg [5:1]fee24;

reg [4:1]timewait1;
reg [4:1]timewait2;
reg [4:1]timewait3;

reg [6:1]timecount1;
reg [9:1]timecount2;
reg [9:1]timecount3;

reg [5:1]begincost;
reg [8:1]feepk;

reg [5:1]feepksave1;
reg [5:1]feepksave2;
reg [5:1]feepksave11;
reg [5:1]feepksave22;

reg [3:1]addlicheng;
reg [5:1]control;

reg clkbase;
reg speed;
reg [8:1]speedcount;
reg clktime;
reg [8:1]clktimecount;
reg [15:1]displaycount;

reg [4:1]displaystate;
reg [4:1]deout1;
reg temp;
reg temp1;
reg [4:1]temp2;
reg [12:1]temp4;
reg [3:1]temp5;


always @(posedge clkbase)                  //时钟产生模块
begin
      speedcount=speedcount+1;
      if(speedcount>=3)     begin    speedcount=0;  speed=1;     end
      else                  begin    speed=0;                    end

      clktimecount=clktimecount+1;
      if(clktimecount>=17)    begin  clktimecount=0;  clktime=1;  end
      else                    begin  clktime=0;                   end
end




always @(posedge clkbase or negedge clr)                   //综合处理模块
begin
if(!clr)
       begin
            if(en==0)
                     begin
                           case(enset)
                           2'b00:  begin  begincost=10;  feepk=8'b00001000;  addlicheng=5; end
                           2'b01:  begin  begincost[4:1]=setall[4:1];   begincost[5]=1'b0; end
                           2'b10:  begin  feepk=setall;                                    end
                           2'b11:  begin  addlicheng=setall[3:1];                          end
                           endcase                                       //预置数模块    
                           flag=3;  
                     end

             temp4=0;
             temp5=0;      
        end
else
begin
if(en==1)
begin
      fee1=fee11+fee21;
      fee2=fee12+fee22;
      fee3=fee13+fee23;
      fee4=fee14+fee24;

      if(fee1>=10)  begin 
                          fee1=fee1-10; fee2=fee2+1;
                          if(fee2>=10)  begin fee2=fee2-10; fee3=fee3+1;       end       
                    end 
     
      if(fee2>=10)  begin 
                          fee2=fee2-10; fee3=fee3+1; 
                          if(fee3>=10)  begin fee3=fee3-10; fee4=fee4+1;       end    
                    end
     
      if(fee3>=10)  begin 
                          fee3=fee3-10; fee4=fee4+1; 
                          if(fee4>=10)  begin fee1=0; fee2=0; fee3=0; fee4=0; flag=3;  end     
                    end 
      
      if(fee4>=10)  begin fee1=0; fee2=0; fee3=0; fee4=0; flag=3;  end  
       
      temp4=temp4+1;
      if(temp4==900)     begin   temp4=0;        temp5=temp5+1;    end
      if(temp5>=4)   begin   temp5=0;        end	 
     
      if(start==0)
      begin
            if(waitselect==0)  
                begin               
                     case(temp5)
				     2'b00:  flag=0; 
				     2'b01:  flag=1;  
				     2'b10:  flag=2; 
				     2'b11:  flag=3; 
				     endcase             
                end
      end 
      

     if(start==1)     
         begin  
               flag=2;
               if(displayselect==0)           
                   begin
                        display[20:17]=licheng4;
                        display[16:13]=licheng3;
                        display[12:9]=licheng2;
                        display[8:5]=15;
                        display[4:1]=licheng1;
                   end      
         end

         if(start==0)
         begin
         if(waitselect==1)
         begin 
              flag=1;
              if(displayselect==0) 
                   begin
                         display[20:17]=0;
                         display[16:13]=timewait3;
                         display[12:9]=15;
                         display[8:5]=timewait2;
                         display[4:1]=timewait1;  
                   end
         end
         end

         if(displayselect==1)    
                 begin
                 display[20:17]=fee4[4:1];
                 display[16:13]=fee3[4:1];
                 display[12:9]=fee2[4:1];
                 display[8:5]=15;
                 display[4:1]=fee1[4:1];
                 end    
end  
end
end

always @(posedge clk)                       //显示输出模块
begin
     displaycount=displaycount+1;
     if(displaycount>=20)  begin  displaycount=0; displaystate=displaystate+1; end
     if(displaystate!=5)   begin  clkbase=0;                                   end

     if(en==0)   
              begin   
                   deout1=0;
                   dot=0; 
                   case(displaystate)
                   4'b0001:   control=5'b00001;
                   4'b0010:   control=5'b00010;  
                   4'b0011:   control=5'b00100; 
                   4'b0100:   control=5'b01000; 
                   4'b0101:   control=5'b10000;
                   endcase       
             end

if(en==1)
       begin
            if(start==0)
                  begin
                       if(waitselect==1)
                           begin
                               if(displayselect==0)
                                   begin
                                        case(displaystate)
                                        4'b0001:   control=5'b00001;
                                        4'b0010:   control=5'b00010;  
                                        4'b0011:   control=5'b00100; 
                                        4'b0100:   control=5'b01000; 
                                        4'b0101:   control=5'b00000;
                                        endcase
                                   end