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📄 texi.vho

📁 在Quartus II 5.0环境下
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SIGNAL \flag[2]~reg0\ : std_logic;
SIGNAL \control[4]~4313\ : std_logic;
SIGNAL \control[1]~reg0\ : std_logic;
SIGNAL \control[2]~reg0\ : std_logic;
SIGNAL \control[3]~reg0\ : std_logic;
SIGNAL \control[4]~reg0\ : std_logic;
SIGNAL \control~4310\ : std_logic;
SIGNAL \control~4309\ : std_logic;
SIGNAL \control~4308\ : std_logic;
SIGNAL \control~4311\ : std_logic;
SIGNAL \control[5]~reg0\ : std_logic;
SIGNAL \dot~reg0\ : std_logic;
SIGNAL \ALT_INV_waitselect~combout\ : std_logic;
SIGNAL \ALT_INV_clr~combout\ : std_logic;
SIGNAL \ALT_INV_displayselect~combout\ : std_logic;

BEGIN

ww_clr <= clr;
ww_start <= start;
ww_set <= set;
ww_setall <= setall;
ww_enset <= enset;
ww_en <= en;
ww_clk <= clk;
ww_waitselect <= waitselect;
ww_displayselect <= displayselect;
deout <= ww_deout;
flag <= ww_flag;
control <= ww_control;
dot <= ww_dot;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\ALT_INV_waitselect~combout\ <= NOT \waitselect~combout\;
\ALT_INV_clr~combout\ <= NOT \clr~combout\;
\ALT_INV_displayselect~combout\ <= NOT \displayselect~combout\;

\clktime~I\ : cyclone_lcell
-- Equation(s):
-- clktime = DFFEAS(GND, GLOBAL(clkbase), VCC, , , \clktimecount[5]\, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => clkbase,
	datac => \clktimecount[5]\,
	aclr => GND,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => clktime);

\speed~I\ : cyclone_lcell
-- Equation(s):
-- speed = DFFEAS(GND, GLOBAL(clkbase), VCC, , , \speedcount[2]\, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => clkbase,
	datac => \speedcount[2]\,
	aclr => GND,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => speed);

\clktimecount[5]~I\ : cyclone_lcell
-- Equation(s):
-- \clktimecount[5]\ = DFFEAS(!\clktimecount[5]\ & \clktimecount[4]\ & \clktimecount[3]\ & \add~9737\, GLOBAL(clkbase), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "4000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => clkbase,
	dataa => \clktimecount[5]\,
	datab => \clktimecount[4]\,
	datac => \clktimecount[3]\,
	datad => \add~9737\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \clktimecount[5]\);

\speedcount[2]~I\ : cyclone_lcell
-- Equation(s):
-- \speedcount[2]\ = DFFEAS(\speedcount[1]\ & !\speedcount[2]\, GLOBAL(clkbase), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0C0C",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => clkbase,
	datab => \speedcount[1]\,
	datac => \speedcount[2]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \speedcount[2]\);

\clktimecount[4]~I\ : cyclone_lcell
-- Equation(s):
-- \clktimecount[4]\ = DFFEAS(!\clktimecount[5]\ & (\clktimecount[4]\ $ (\clktimecount[3]\ & \add~9737\)), GLOBAL(clkbase), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "1444",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => clkbase,
	dataa => \clktimecount[5]\,
	datab => \clktimecount[4]\,
	datac => \clktimecount[3]\,
	datad => \add~9737\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \clktimecount[4]\);

\clktimecount[3]~I\ : cyclone_lcell
-- Equation(s):
-- \clktimecount[3]\ = DFFEAS(!\clktimecount[5]\ & (\clktimecount[3]\ $ (\clktimecount[1]\ & \clktimecount[2]\)), GLOBAL(clkbase), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "060C",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => clkbase,
	dataa => \clktimecount[1]\,
	datab => \clktimecount[3]\,
	datac => \clktimecount[5]\,
	datad => \clktimecount[2]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \clktimecount[3]\);

\clktimecount[1]~I\ : cyclone_lcell
-- Equation(s):
-- \clktimecount[1]\ = DFFEAS(!\clktimecount[1]\ & (!\clktimecount[5]\), GLOBAL(clkbase), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0505",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => clkbase,
	dataa => \clktimecount[1]\,
	datac => \clktimecount[5]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \clktimecount[1]\);

\clktimecount[2]~I\ : cyclone_lcell
-- Equation(s):
-- \clktimecount[2]\ = DFFEAS(!\clktimecount[5]\ & (\clktimecount[1]\ $ \clktimecount[2]\), GLOBAL(clkbase), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "050A",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => clkbase,
	dataa => \clktimecount[1]\,
	datac => \clktimecount[5]\,
	datad => \clktimecount[2]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \clktimecount[2]\);

\add~9737_I\ : cyclone_lcell
-- Equation(s):
-- \add~9737\ = \clktimecount[1]\ & \clktimecount[2]\

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "F000",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datac => \clktimecount[1]\,
	datad => \clktimecount[2]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \add~9737\);

\speedcount[1]~I\ : cyclone_lcell
-- Equation(s):
-- \speedcount[1]\ = DFFEAS(!\speedcount[1]\ & !\speedcount[2]\, GLOBAL(clkbase), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0303",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => clkbase,
	datab => \speedcount[1]\,
	datac => \speedcount[2]\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \speedcount[1]\);

\clk~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_clk,
	combout => \clk~combout\);

\en~I\ : cyclone_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_en,
	combout => \en~combout\);

\displaycount[3]~I\ : cyclone_lcell
-- Equation(s):
-- \displaycount[3]\ = DFFEAS(!\add~9157\ & \add~9142\ & (!\add~9152\), GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0044",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	dataa => \add~9157\,
	datab => \add~9142\,
	datad => \add~9152\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \displaycount[3]\);

\add~9555_I\ : cyclone_lcell
-- Equation(s):
-- \add~9555\ = !\displaycount[1]\
-- \add~9557\ = CARRY(\displaycount[1]\)
-- \add~9557COUT1_9883\ = CARRY(\displaycount[1]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "33CC",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => \displaycount[1]\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \add~9555\,
	cout0 => \add~9557\,
	cout1 => \add~9557COUT1_9883\);

\displaycount[1]~I\ : cyclone_lcell
-- Equation(s):
-- \displaycount[1]\ = DFFEAS(\LessThan~2744\ & \add~9555\, GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "F000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	datac => \LessThan~2744\,
	datad => \add~9555\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \displaycount[1]\);

\add~9382_I\ : cyclone_lcell
-- Equation(s):
-- \add~9382\ = \displaycount[2]\ $ \add~9557\
-- \add~9384\ = CARRY(!\add~9557\ # !\displaycount[2]\)
-- \add~9384COUT1_9884\ = CARRY(!\add~9557COUT1_9883\ # !\displaycount[2]\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "3C3F",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "comb_only")
-- pragma translate_on
PORT MAP (
	datab => \displaycount[2]\,
	cin0 => \add~9557\,
	cin1 => \add~9557COUT1_9883\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	combout => \add~9382\,
	cout0 => \add~9384\,
	cout1 => \add~9384COUT1_9884\);

\displaycount[2]~I\ : cyclone_lcell
-- Equation(s):
-- \displaycount[2]\ = DFFEAS(\LessThan~2744\ & (\add~9382\), GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "A0A0",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => \clk~combout\,
	dataa => \LessThan~2744\,
	datac => \add~9382\,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => \displaycount[2]\);

\add~9142_I\ : cyclone_lcell
-- Equation(s):
-- \add~9142\ = \displaycount[3]\ $ !\add~9384\
-- \add~9144\ = CARRY(\displaycount[3]\ & !\add~9384\)
-- \add~9144COUT1\ = CARRY(\displaycount[3]\ & !\add~9384COUT1_9884\)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
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