texi.vho

在Quartus II 5.0环境下

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

-- DATE "10/18/2007 23:55:19"

-- 
-- Device: Altera EP1C6Q240C8 Package PQFP240
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, cyclone;
USE IEEE.std_logic_1164.all;
USE cyclone.cyclone_components.all;

ENTITY 	texi IS
    PORT (
	clr : IN std_logic;
	start : IN std_logic;
	set : IN std_logic;
	setall : IN std_logic_vector(8 DOWNTO 1);
	enset : IN std_logic_vector(2 DOWNTO 1);
	en : IN std_logic;
	clk : IN std_logic;
	waitselect : IN std_logic;
	displayselect : IN std_logic;
	deout : OUT std_logic_vector(7 DOWNTO 1);
	flag : OUT std_logic_vector(2 DOWNTO 1);
	control : OUT std_logic_vector(5 DOWNTO 1);
	dot : OUT std_logic
	);
END texi;

ARCHITECTURE structure OF texi IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clr : std_logic;
SIGNAL ww_start : std_logic;
SIGNAL ww_set : std_logic;
SIGNAL ww_setall : std_logic_vector(8 DOWNTO 1);
SIGNAL ww_enset : std_logic_vector(2 DOWNTO 1);
SIGNAL ww_en : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_waitselect : std_logic;
SIGNAL ww_displayselect : std_logic;
SIGNAL ww_deout : std_logic_vector(7 DOWNTO 1);
SIGNAL ww_flag : std_logic_vector(2 DOWNTO 1);
SIGNAL ww_control : std_logic_vector(5 DOWNTO 1);
SIGNAL ww_dot : std_logic;
SIGNAL \deout1[1]\ : std_logic;
SIGNAL \deout1[2]\ : std_logic;
SIGNAL \deout1[3]\ : std_logic;
SIGNAL \deout1[4]\ : std_logic;
SIGNAL clktime : std_logic;
SIGNAL speed : std_logic;
SIGNAL \add~9503\ : std_logic;
SIGNAL \add~9550\ : std_logic;
SIGNAL \clktimecount[5]\ : std_logic;
SIGNAL \speedcount[2]\ : std_logic;
SIGNAL \clktimecount[4]\ : std_logic;
SIGNAL \clktimecount[3]\ : std_logic;
SIGNAL \clktimecount[1]\ : std_logic;
SIGNAL \clktimecount[2]\ : std_logic;
SIGNAL \add~9737\ : std_logic;
SIGNAL \speedcount[1]\ : std_logic;
SIGNAL \clk~combout\ : std_logic;
SIGNAL \en~combout\ : std_logic;
SIGNAL \displaycount[3]\ : std_logic;
SIGNAL \add~9555\ : std_logic;
SIGNAL \displaycount[1]\ : std_logic;
SIGNAL \add~9557\ : std_logic;
SIGNAL \add~9557COUT1_9883\ : std_logic;
SIGNAL \add~9382\ : std_logic;
SIGNAL \displaycount[2]\ : std_logic;
SIGNAL \add~9384\ : std_logic;
SIGNAL \add~9384COUT1_9884\ : std_logic;
SIGNAL \add~9142\ : std_logic;
SIGNAL \add~9144\ : std_logic;
SIGNAL \add~9144COUT1\ : std_logic;
SIGNAL \add~9147\ : std_logic;
SIGNAL \displaycount[5]\ : std_logic;
SIGNAL \add~9152\ : std_logic;
SIGNAL \displaycount[4]\ : std_logic;
SIGNAL \add~9149\ : std_logic;
SIGNAL \add~9154\ : std_logic;
SIGNAL \add~9154COUT1_9885\ : std_logic;
SIGNAL \add~9157\ : std_logic;
SIGNAL \LessThan~2744\ : std_logic;
SIGNAL \displaystate[3]\ : std_logic;
SIGNAL \displaystate[1]\ : std_logic;
SIGNAL \displaystate[2]\ : std_logic;
SIGNAL \control[4]~4303\ : std_logic;
SIGNAL \start~combout\ : std_logic;
SIGNAL \deout1~2579\ : std_logic;
SIGNAL \waitselect~combout\ : std_logic;
SIGNAL \deout1~2580\ : std_logic;
SIGNAL \clr~combout\ : std_logic;
SIGNAL \control[4]~4305\ : std_logic;
SIGNAL \timecount3[2]\ : std_logic;
SIGNAL \add~9468\ : std_logic;
SIGNAL \timecount3[1]\ : std_logic;
SIGNAL \add~9470\ : std_logic;
SIGNAL \add~9470COUT1_9871\ : std_logic;
SIGNAL \add~9473\ : std_logic;
SIGNAL \timecount3[8]\ : std_logic;
SIGNAL \add~9475\ : std_logic;
SIGNAL \add~9475COUT1_9872\ : std_logic;
SIGNAL \add~9465\ : std_logic;
SIGNAL \add~9465COUT1_9873\ : std_logic;
SIGNAL \add~9478\ : std_logic;
SIGNAL \timecount3[4]\ : std_logic;
SIGNAL \add~9480\ : std_logic;
SIGNAL \add~9480COUT1\ : std_logic;
SIGNAL \add~9483\ : std_logic;
SIGNAL \timecount3[5]\ : std_logic;
SIGNAL \add~9485\ : std_logic;
SIGNAL \add~9488\ : std_logic;
SIGNAL \timecount3[6]\ : std_logic;
SIGNAL \add~9490\ : std_logic;
SIGNAL \add~9490COUT1_9874\ : std_logic;
SIGNAL \add~9493\ : std_logic;
SIGNAL \timecount3[7]\ : std_logic;
SIGNAL \add~9495\ : std_logic;
SIGNAL \add~9495COUT1_9875\ : std_logic;
SIGNAL \add~9498\ : std_logic;
SIGNAL \rtl~1134\ : std_logic;
SIGNAL \timecount3[3]\ : std_logic;
SIGNAL \add~9463\ : std_logic;
SIGNAL \rtl~1133\ : std_logic;
SIGNAL \timecount3[9]\ : std_logic;
SIGNAL \add~9500\ : std_logic;
SIGNAL \add~9500COUT1_9876\ : std_logic;
SIGNAL \add~9458\ : std_logic;
SIGNAL \licheng1[1]~243\ : std_logic;
SIGNAL \licheng4[1]\ : std_logic;
SIGNAL \licheng1[1]\ : std_logic;
SIGNAL \licheng1[2]\ : std_logic;
SIGNAL \add~9591\ : std_logic;
SIGNAL \add~9596\ : std_logic;
SIGNAL \licheng1[4]\ : std_logic;
SIGNAL \add~9595\ : std_logic;
SIGNAL \licheng1[3]\ : std_logic;
SIGNAL \LessThan~2756\ : std_logic;
SIGNAL \licheng2[1]\ : std_logic;
SIGNAL \add~9450\ : std_logic;
SIGNAL \licheng2[3]\ : std_logic;
SIGNAL \rtl~3\ : std_logic;
SIGNAL \add~9549\ : std_logic;
SIGNAL \licheng2~113\ : std_logic;
SIGNAL \licheng2[2]\ : std_logic;
SIGNAL \rtl~1130\ : std_logic;
SIGNAL \licheng2[4]\ : std_logic;
SIGNAL \add~9451\ : std_logic;
SIGNAL \licheng3[1]\ : std_logic;
SIGNAL \add~9452\ : std_logic;
SIGNAL \rtl~4\ : std_logic;
SIGNAL \licheng3[2]\ : std_logic;
SIGNAL \add~9598\ : std_logic;
SIGNAL \licheng3[4]\ : std_logic;
SIGNAL \rtl~1131\ : std_logic;
SIGNAL \add~9456\ : std_logic;
SIGNAL \add~9453\ : std_logic;
SIGNAL \add~9457\ : std_logic;
SIGNAL \licheng4[4]\ : std_logic;
SIGNAL \licheng4[3]\ : std_logic;
SIGNAL \add~9454\ : std_logic;
SIGNAL \licheng4[2]\ : std_logic;
SIGNAL \add~9455\ : std_logic;
SIGNAL \rtl~1132\ : std_logic;
SIGNAL \licheng3[3]\ : std_logic;
SIGNAL \timewait3[1]~11\ : std_logic;
SIGNAL \timecount1[6]\ : std_logic;
SIGNAL \timecount1[2]\ : std_logic;
SIGNAL \add~9731\ : std_logic;
SIGNAL \timecount1[4]\ : std_logic;
SIGNAL \add~9561\ : std_logic;
SIGNAL \timecount1[5]\ : std_logic;
SIGNAL \add~9562\ : std_logic;
SIGNAL \rtl~7\ : std_logic;
SIGNAL \timecount1[1]\ : std_logic;
SIGNAL \add~9560\ : std_logic;
SIGNAL \timecount1[3]\ : std_logic;
SIGNAL \rtl~1137\ : std_logic;
SIGNAL \add~9585\ : std_logic;
SIGNAL \timewait1[4]~686\ : std_logic;
SIGNAL \timewait1~691\ : std_logic;
SIGNAL \LessThan~2765\ : std_logic;
SIGNAL \LessThan~2764\ : std_logic;
SIGNAL \LessThan~2766\ : std_logic;
SIGNAL \add~9563\ : std_logic;
SIGNAL \timewait1[1]\ : std_logic;
SIGNAL \add~9583\ : std_logic;
SIGNAL \add~9592\ : std_logic;
SIGNAL \timewait1[2]\ : std_logic;
SIGNAL \timewait1~694\ : std_logic;
SIGNAL \add~9565\ : std_logic;
SIGNAL \add~9565COUT1_9886\ : std_logic;
SIGNAL \add~9578\ : std_logic;
SIGNAL \add~9594\ : std_logic;
SIGNAL \timewait1[3]\ : std_logic;
SIGNAL \timewait1~692\ : std_logic;
SIGNAL \add~9580\ : std_logic;
SIGNAL \add~9580COUT1\ : std_logic;
SIGNAL \add~9568\ : std_logic;
SIGNAL \add~9584\ : std_logic;
SIGNAL \timewait1[4]\ : std_logic;
SIGNAL \timewait1~693\ : std_logic;
SIGNAL \add~9570\ : std_logic;
SIGNAL \add~9570COUT1_9887\ : std_logic;
SIGNAL \add~9573\ : std_logic;
SIGNAL \rtl~1139\ : std_logic;
SIGNAL \rtl~1138\ : std_logic;
SIGNAL \rtl~1140\ : std_logic;
SIGNAL \LessThan~2759\ : std_logic;
SIGNAL \timewait2[1]\ : std_logic;
SIGNAL \add~9593\ : std_logic;
SIGNAL \timewait2[2]\ : std_logic;
SIGNAL \add~9597\ : std_logic;
SIGNAL \timewait2[3]\ : std_logic;
SIGNAL \timewait2[4]\ : std_logic;
SIGNAL \rtl~1141\ : std_logic;
SIGNAL \rtl~9\ : std_logic;
SIGNAL \add~9430\ : std_logic;
SIGNAL \timewait3[1]\ : std_logic;
SIGNAL \add~9432\ : std_logic;
SIGNAL \add~9432COUT1_9869\ : std_logic;
SIGNAL \add~9435\ : std_logic;
SIGNAL \timewait3[4]\ : std_logic;
SIGNAL \add~9437COUT1\ : std_logic;
SIGNAL \add~9442\ : std_logic;
SIGNAL \add~9442COUT1_9870\ : std_logic;
SIGNAL \add~9445\ : std_logic;
SIGNAL \timewait3[2]\ : std_logic;
SIGNAL \add~9437\ : std_logic;
SIGNAL \add~9440\ : std_logic;
SIGNAL \timewait3[3]\ : std_logic;
SIGNAL \add~9726\ : std_logic;
SIGNAL \fee24[1]\ : std_logic;
SIGNAL \add~9728\ : std_logic;
SIGNAL \add~9728COUT1_9903\ : std_logic;
SIGNAL \add~9601\ : std_logic;
SIGNAL \add~9601COUT1\ : std_logic;
SIGNAL \add~9604\ : std_logic;
SIGNAL \fee24[3]\ : std_logic;
SIGNAL \add~9606\ : std_logic;
SIGNAL \add~9606COUT1_9904\ : std_logic;
SIGNAL \add~9609\ : std_logic;
SIGNAL \fee24[2]\ : std_logic;
SIGNAL \add~9599\ : std_logic;
SIGNAL \fee24[4]\ : std_logic;
SIGNAL \add~9611\ : std_logic;
SIGNAL \add~9611COUT1_9905\ : std_logic;
SIGNAL \add~9614\ : std_logic;
SIGNAL \LessThan~2760\ : std_logic;
SIGNAL \fee22[1]~964\ : std_logic;
SIGNAL \timecount2[9]~27\ : std_logic;
SIGNAL \timecount2[2]\ : std_logic;
SIGNAL \add~9659\ : std_logic;
SIGNAL \timecount2[1]\ : std_logic;
SIGNAL \add~9661\ : std_logic;
SIGNAL \add~9661COUT1_9894\ : std_logic;
SIGNAL \add~9664\ : std_logic;
SIGNAL \timecount2[3]\ : std_logic;
SIGNAL \add~9666\ : std_logic;
SIGNAL \add~9666COUT1_9895\ : std_logic;
SIGNAL \add~9649\ : std_logic;
SIGNAL \timecount2[4]\ : std_logic;
SIGNAL \add~9651\ : std_logic;
SIGNAL \add~9651COUT1_9896\ : std_logic;
SIGNAL \add~9654\ : std_logic;
SIGNAL \rtl~1144\ : std_logic;
SIGNAL \timecount2[8]\ : std_logic;
SIGNAL \add~9656\ : std_logic;
SIGNAL \add~9656COUT1\ : std_logic;
SIGNAL \add~9674\ : std_logic;
SIGNAL \timecount2[5]\ : std_logic;
SIGNAL \add~9676\ : std_logic;
SIGNAL \add~9669\ : std_logic;
SIGNAL \timecount2[6]\ : std_logic;
SIGNAL \add~9671\ : std_logic;
SIGNAL \add~9671COUT1_9897\ : std_logic;
SIGNAL \add~9679\ : std_logic;
SIGNAL \timecount2[7]\ : std_logic;
SIGNAL \add~9681\ : std_logic;
SIGNAL \add~9681COUT1_9898\ : std_logic;
SIGNAL \add~9684\ : std_logic;
SIGNAL \rtl~1145\ : std_logic;
SIGNAL \timecount2[9]\ : std_logic;
SIGNAL \add~9686\ : std_logic;
SIGNAL \add~9686COUT1_9899\ : std_logic;
SIGNAL \add~9644\ : std_logic;
SIGNAL \rtl~1146\ : std_logic;
SIGNAL \add~9692\ : std_logic;
SIGNAL \fee22~971\ : std_logic;
SIGNAL \LessThan~2770\ : std_logic;
SIGNAL \LessThan~2771\ : std_logic;
SIGNAL \LessThan~2767\ : std_logic;
SIGNAL \LessThan~2768\ : std_logic;
SIGNAL \LessThan~2769\ : std_logic;
SIGNAL \LessThan~2772\ : std_logic;
SIGNAL \add~9624\ : std_logic;
SIGNAL \fee22[1]\ : std_logic;
SIGNAL \fee22~973\ : std_logic;
SIGNAL \add~9626\ : std_logic;
SIGNAL \add~9626COUT1_9891\ : std_logic;
SIGNAL \add~9634\ : std_logic;
SIGNAL \add~9695\ : std_logic;
SIGNAL \fee22[2]\ : std_logic;
SIGNAL \add~9691\ : std_logic;
SIGNAL \add~9693\ : std_logic;
SIGNAL \fee22~972\ : std_logic;
SIGNAL \add~9636\ : std_logic;
SIGNAL \add~9636COUT1\ : std_logic;
SIGNAL \add~9629\ : std_logic;
SIGNAL \fee22[3]\ : std_logic;
SIGNAL \add~9694\ : std_logic;
SIGNAL \add~9689\ : std_logic;
SIGNAL \fee22~974\ : std_logic;
SIGNAL \add~9631\ : std_logic;
SIGNAL \add~9631COUT1_9892\ : std_logic;
SIGNAL \add~9639\ : std_logic;
SIGNAL \fee22[4]\ : std_logic;
SIGNAL \fee22~970\ : std_logic;
SIGNAL \add~9641\ : std_logic;
SIGNAL \add~9641COUT1_9893\ : std_logic;
SIGNAL \add~9619\ : std_logic;
SIGNAL \fee22[5]\ : std_logic;
SIGNAL \add~9690\ : std_logic;
SIGNAL \rtl~1147\ : std_logic;
SIGNAL \rtl~1142\ : std_logic;
SIGNAL \rtl~1143\ : std_logic;
SIGNAL \rtl~1148\ : std_logic;
SIGNAL \fee23[1]\ : std_logic;
SIGNAL \add~9696\ : std_logic;
SIGNAL \fee23[3]\ : std_logic;
SIGNAL \add~9723\ : std_logic;
SIGNAL \fee23[4]\ : std_logic;
SIGNAL \fee23[5]\ : std_logic;
SIGNAL \add~9724\ : std_logic;
SIGNAL \rtl~1149\ : std_logic;
SIGNAL \rtl~1150\ : std_logic;
SIGNAL \fee23[2]\ : std_logic;
SIGNAL \add~9718\ : std_logic;
SIGNAL \enset[2]~combout\ : std_logic;
SIGNAL \setall[2]~combout\ : std_logic;
SIGNAL \enset[1]~combout\ : std_logic;
SIGNAL \Select~1163\ : std_logic;
SIGNAL \always1~14\ : std_logic;
SIGNAL \addlicheng[2]\ : std_logic;
SIGNAL \licheng2~114\ : std_logic;
SIGNAL \rtl~1135\ : std_logic;
SIGNAL \licheng2~116\ : std_logic;
SIGNAL \licheng2~115\ : std_logic;
SIGNAL \setall[1]~combout\ : std_logic;
SIGNAL \Select~1165\ : std_logic;
SIGNAL \addlicheng[1]\ : std_logic;
SIGNAL \setall[3]~combout\ : std_logic;
SIGNAL \Select~1164\ : std_logic;
SIGNAL \addlicheng[3]\ : std_logic;
SIGNAL \rtl~1136\ : std_logic;
SIGNAL temp1 : std_logic;
SIGNAL \fee14[5]~10\ : std_logic;
SIGNAL \fee14[1]\ : std_logic;
SIGNAL \add~9720\ : std_logic;
SIGNAL \add~9720COUT1_9900\ : std_logic;
SIGNAL \add~9518\ : std_logic;
SIGNAL \fee14[2]\ : std_logic;
SIGNAL \add~9520\ : std_logic;
SIGNAL \add~9520COUT1\ : std_logic;
SIGNAL \add~9525\ : std_logic;
SIGNAL \add~9525COUT1_9901\ : std_logic;
SIGNAL \add~9530\ : std_logic;
SIGNAL \add~9530COUT1_9902\ : std_logic;
SIGNAL \add~9533\ : std_logic;
SIGNAL \fee14[4]\ : std_logic;
SIGNAL \add~9528\ : std_logic;
SIGNAL \fee14[3]\ : std_logic;
SIGNAL \add~9523\ : std_logic;
SIGNAL \LessThan~2757\ : std_logic;
SIGNAL \setall[4]~combout\ : std_logic;
SIGNAL \Select~1168\ : std_logic;
SIGNAL \always1~1\ : std_logic;
SIGNAL \begincost[4]\ : std_logic;
SIGNAL \Select~1167\ : std_logic;
SIGNAL \begincost[2]\ : std_logic;
SIGNAL \Select~1166\ : std_logic;
SIGNAL \begincost[3]\ : std_logic;
SIGNAL \LessThan~2763\ : std_logic;
SIGNAL \setall[7]~combout\ : std_logic;
SIGNAL \Select~1171\ : std_logic;
SIGNAL \always1~3\ : std_logic;
SIGNAL \feepk[7]\ : std_logic;
SIGNAL \setall[5]~combout\ : std_logic;
SIGNAL \Select~1173\ : std_logic;
SIGNAL \feepk[5]\ : std_logic;
SIGNAL \feepk[4]\ : std_logic;
SIGNAL \feepk[3]\ : std_logic;
SIGNAL \feepk[2]\ : std_logic;
SIGNAL \setall[6]~combout\ : std_logic;
SIGNAL \Select~1170\ : std_logic;
SIGNAL \feepk[6]\ : std_logic;
SIGNAL \add~9841\ : std_logic;
SIGNAL \feepksave22~359\ : std_logic;
SIGNAL \feepksave22[2]\ : std_logic;
SIGNAL \setall[8]~combout\ : std_logic;
SIGNAL \Select~1172\ : std_logic;
SIGNAL \feepk[8]\ : std_logic;
SIGNAL \feepksave22~361\ : std_logic;
SIGNAL \feepksave22[3]\ : std_logic;
SIGNAL \feepksave11~445\ : std_logic;
SIGNAL \feepksave11[3]\ : std_logic;
SIGNAL \feepksave11~444\ : std_logic;
SIGNAL \feepksave11[2]\ : std_logic;
SIGNAL \feepksave11~446\ : std_logic;
SIGNAL \feepksave11[4]\ : std_logic;
SIGNAL \feepksave1~225\ : std_logic;