texi.map.rpt

在Quartus II 5.0环境下

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Thu Oct 18 23:55:26 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off texi -c texi
Info: Found 1 design units, including 1 entities, in source file texi.v
    Info: Found entity 1: texi
Info: Elaborating entity "texi" for the top level hierarchy
Info (10035): Verilog HDL or VHDL information at texi.v(2): object "set" declared but not used
Warning (10230): Verilog HDL assignment warning at texi.v(73): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at texi.v(77): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at texi.v(113): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(114): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(118): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(119): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(123): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(129): truncated value with size 32 to match size of target (12)
Warning (10230): Verilog HDL assignment warning at texi.v(130): truncated value with size 32 to match size of target (3)
Warning (10270): Verilog HDL statement warning at texi.v(137): incomplete Case Statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at texi.v(85): variable "begincost" may not be assigned a new value in every possible path through the Always Construct.  Variable "begincost" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10240): Verilog HDL Always Construct warning at texi.v(85): variable "feepk" may not be assigned a new value in every possible path through the Always Construct.  Variable "feepk" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10240): Verilog HDL Always Construct warning at texi.v(85): variable "addlicheng" may not be assigned a new value in every possible path through the Always Construct.  Variable "addlicheng" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10230): Verilog HDL assignment warning at texi.v(190): truncated value with size 32 to match size of target (15)
Warning (10230): Verilog HDL assignment warning at texi.v(191): truncated value with size 32 to match size of target (4)
Warning (10270): Verilog HDL statement warning at texi.v(198): incomplete Case Statement has no default case item
Warning (10270): Verilog HDL statement warning at texi.v(215): incomplete Case Statement has no default case item
Warning (10270): Verilog HDL statement warning at texi.v(226): incomplete Case Statement has no default case item
Warning (10270): Verilog HDL statement warning at texi.v(235): incomplete Case Statement has no default case item
Warning (10270): Verilog HDL statement warning at texi.v(249): incomplete Case Statement has no default case item
Warning (10270): Verilog HDL statement warning at texi.v(257): incomplete Case Statement has no default case item
Warning (10270): Verilog HDL statement warning at texi.v(272): incomplete Case Statement has no default case item
Warning (10230): Verilog HDL assignment warning at texi.v(320): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(331): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(334): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(335): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(347): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at texi.v(350): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at texi.v(352): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at texi.v(353): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at texi.v(354): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at texi.v(361): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(363): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(364): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(376): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at texi.v(388): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(389): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(393): truncated value with size 32 to match size of target (5)
Warning (10240): Verilog HDL Always Construct warning at texi.v(311): variable "feepksave22" may not be assigned a new value in every possible path through the Always Construct.  Variable "feepksave22" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10240): Verilog HDL Always Construct warning at texi.v(311): variable "feepksave11" may not be assigned a new value in every possible path through the Always Construct.  Variable "feepksave11" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10230): Verilog HDL assignment warning at texi.v(420): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at texi.v(421): truncated value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at texi.v(422): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at texi.v(423): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(428): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at texi.v(429): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(434): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at texi.v(435): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at texi.v(438): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(439): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at texi.v(440): truncated value with size 32 to match size of target (5)
Warning: Reduced register "fee21[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "fee21[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "fee21[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "fee21[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "fee21[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "displaystate[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "displaycount[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "displaycount[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "displaycount[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "displaycount[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "fee24[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "fee14[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "clktimecount[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "clktimecount[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "clktimecount[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "temp" with stuck data_in port to stuck value GND
Warning: Reduced register "fee4[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "speedcount[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "speedcount[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "speedcount[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "speedcount[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "temp5[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "displaycount[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "displaycount[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "displaycount[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "speedcount[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "speedcount[3]" with stuck data_in port to stuck value GND
Warning: Latch addlicheng[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[1]
Warning: Latch addlicheng[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[1]
Warning: Latch addlicheng[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[1]
Warning: Latch begincost[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[2]
Warning: Latch begincost[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[2]
Warning: Latch begincost[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[2]
Warning: Latch begincost[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[2]
Warning: Latch feepk[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[1]
Warning: Latch feepk[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[1]
Warning: Latch feepk[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[1]
Warning: Latch feepk[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[1]
Warning: Latch feepk[8] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[1]
Warning: Latch feepk[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[1]
Warning: Latch feepk[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[1]
Warning: Latch feepk[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal enset[1]
Warning: Reduced register "displaycount[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "displaycount[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "displaycount[8]" with stuck data_in port to stuck value GND
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "set"
Info: Implemented 625 device resources after synthesis - the final resource count might be different
    Info: Implemented 17 input pins
    Info: Implemented 15 output pins
    Info: Implemented 593 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 113 warnings
    Info: Processing ended: Thu Oct 18 23:55:37 2007
    Info: Elapsed time: 00:00:11