texi.qsf

在Quartus II 5.0环境下

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		texi_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY texi
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:25:16  OCTOBER 12, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 5.1
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_timing_analysis
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_timing_analysis
set_global_assignment -name VERILOG_FILE texi.v
set_location_assignment PIN_152 -to clk
set_location_assignment PIN_94 -to control[1]
set_location_assignment PIN_93 -to control[2]
set_location_assignment PIN_88 -to control[3]
set_location_assignment PIN_87 -to control[4]
set_location_assignment PIN_86 -to control[5]
set_location_assignment PIN_184 -to deout[1]
set_location_assignment PIN_183 -to deout[2]
set_location_assignment PIN_182 -to deout[3]
set_location_assignment PIN_181 -to deout[4]
set_location_assignment PIN_180 -to deout[5]
set_location_assignment PIN_179 -to deout[6]
set_location_assignment PIN_178 -to deout[7]
set_location_assignment PIN_2 -to en
set_location_assignment PIN_17 -to start
set_location_assignment PIN_18 -to waitselect
set_location_assignment PIN_14 -to displayselect
set_location_assignment PIN_16 -to enset[1]
set_location_assignment PIN_15 -to enset[2]
set_location_assignment PIN_44 -to flag[1]
set_location_assignment PIN_43 -to flag[2]
set_location_assignment PIN_42 -to setall[1]
set_location_assignment PIN_41 -to setall[2]
set_location_assignment PIN_39 -to setall[3]
set_location_assignment PIN_38 -to setall[4]
set_location_assignment PIN_23 -to setall[5]
set_location_assignment PIN_21 -to setall[6]
set_location_assignment PIN_20 -to setall[7]
set_location_assignment PIN_19 -to setall[8]
set_location_assignment PIN_236 -to clr
set_location_assignment PIN_185 -to dot