count3.vhd

来自「vhdl实现的计数器,可以从0记到999,该代码使用模块化设计思想,开发工具mu」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity count3 is
		port(reset: in std_logic;
			 clk : in std_logic;
			 sel : out std_logic_vector(2 downto 0));
end count3;
architecture rtl of count3 is
	signal sel_temp : std_logic_vector(2 downto 0);
begin
	process(clk)
	begin
		if(clk'event and clk='1') then
			if(reset='1')then
				sel_temp<=(others=>'0');
			elsif(sel_temp="010") then
				sel_temp<=(others=>'0');
			else
				sel_temp<=sel_temp+1;
			end if;
		end if;
		sel<=sel_temp;
	end process;
end rtl;