seg7.vhd

来自「vhdl实现的计数器,可以从0记到999,该代码使用模块化设计思想,开发工具mu」· VHDL 代码 · 共 25 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY seg7 IS
	PORT(q : IN std_logic_vector(3 DOWNTO 0);
		segment : OUT std_logic_vector(6 DOWNTO 0));
END seg7;
ARCHITECTURE rt1 OF seg7 IS
BEGIN
	PROCESS(q)
BEGIN
	CASE q IS
		WHEN "0000"=>segment<="0111111";
		WHEN "0001"=>segment<="0000110";
		WHEN "0010"=>segment<="1011011";
		WHEN "0011"=>segment<="1001111";
		WHEN "0100"=>segment<="1100110";
		WHEN "0101"=>segment<="1111101";
		WHEN "0110"=>segment<="0100111";
		WHEN "1000"=>segment<="1111111";
		WHEN "1001"=>segment<="1101111";
		WHEN OTHERS=>segment<="1111001";
	END CASE;
END PROCESS;
END rt1;