display.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is
port(cnumina,cnuminb,cnuminc,cnumind: in integer range 0 to 90;
	 clk2 : in std_logic;
	 ct : out std_logic_vector(7 downto 0);
	 segout : out std_logic_vector(6 downto 0));
end;
architecture ctr of display is
signal q: integer range 0 to 7;
signal w,xa,ya,xb,yb,xc,yc,xd,yd: integer range 0 to 9;
begin

process(cnumina,clk2)
variable ma,na,mb,nb,mc,nc,md,nd: integer range 0 to 9;
begin
if rising_edge(clk2) then 
		if q=7 then q<=0;	
			ma:=cnumina rem 10;
			na:=(cnumina-ma)/10;
			mb:=cnuminb rem 10;
			nb:=(cnuminb-mb)/10;
			mc:=cnuminc rem 10;
			nc:=(cnuminc-mc)/10;
			md:=cnumind rem 10;
			nd:=(cnumind-md)/10;
			
		else q<=q+1;
			ma:=cnumina rem 10;
			na:=(cnumina-ma)/10;
			mb:=cnuminb rem 10;
			nb:=(cnuminb-mb)/10;
			mc:=cnuminc rem 10;
			nc:=(cnuminc-mc)/10;
			md:=cnumind rem 10;
			nd:=(cnumind-md)/10;
end if;
end if;
xa<=ma;
ya<=na;
xb<=mb;
yb<=nb;
xc<=mc;
yc<=nc;
xd<=md;
yd<=nd;
end process;
process(q,xa,ya,xb,yb,xc,yc,xd,yd)
begin
case q is
	when 0 => ct<="00000001"; w<=xa;
	when 1 => ct<="00000010"; w<=ya;
	when 2 => ct<="00000100"; w<=xb;
	when 3 => ct<="00001000"; w<=yb;
	when 4 => ct<="00010000"; w<=xc;
	when 5 => ct<="00100000"; w<=yc;
	when 6 => ct<="01000000"; w<=xd;
	when 7 => ct<="10000000"; w<=yd;
end case;
end process;

process(w)
variable seg:std_logic_vector(6 downto 0);
begin
case w is
  when  0 =>seg:="1111110";--/1000000
  when  1 =>seg:="0110000";--/1111001
  when  2 =>seg:="1101101";--/0100100 
  when  3 =>seg:="1111001";--/0110000
  when  4 =>seg:="0110011";--/0011001
  when  5 =>seg:="1011011";--/0010010
  when  6 =>seg:="1011111";--/0000010
  when  7 =>seg:="1110000";--/1111000
  when  8 =>seg:="1111111";--/0000000
  when  9 =>seg:="1111011";--/0010000
  when others =>null;
end case;
segout<=seg;
end process;
end ctr;