prev_cmp_gmaj.map.qmsg

vhdl实现交通灯设计,可以实现十字路口处交通控制,开发工具quartus

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 15 17:00:36 2008 " "Info: Processing started: Mon Dec 15 17:00:36 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gamj -c gmaj " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gamj -c gmaj" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CLK.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CLK.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CLK-ctr " "Info: Found design unit 1: CLK-ctr" {  } { { "CLK.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/CLK.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 CLK " "Info: Found entity 1: CLK" {  } { { "CLK.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/CLK.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-ctr " "Info: Found design unit 1: counter-ctr" {  } { { "counter.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/counter.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/counter.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter1-ctr " "Info: Found design unit 1: counter1-ctr" {  } { { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/counter1.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter1 " "Info: Found entity 1: counter1" {  } { { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/counter1.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display-ctr " "Info: Found design unit 1: display-ctr" {  } { { "display.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/display.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "display.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/display.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "traffic.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file traffic.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 traffic " "Info: Found entity 1: traffic" {  } { { "traffic.bdf" "" { Schematic "F:/vhdl traffic light/traffic gmaj/traffic.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter2-ctr " "Info: Found design unit 1: counter2-ctr" {  } { { "counter2.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/counter2.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter2 " "Info: Found entity 1: counter2" {  } { { "counter2.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/counter2.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter3.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter3.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter3-ctr " "Info: Found design unit 1: counter3-ctr" {  } { { "counter3.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/counter3.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter3 " "Info: Found entity 1: counter3" {  } { { "counter3.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/counter3.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cctr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cctr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cctr-ctr " "Info: Found design unit 1: cctr-ctr" {  } { { "cctr.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 cctr " "Info: Found entity 1: cctr" {  } { { "cctr.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cctr1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cctr1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cctr1-ctr " "Info: Found design unit 1: cctr1-ctr" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 cctr1 " "Info: Found entity 1: cctr1" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gmaj.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file gmaj.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 gmaj " "Info: Found entity 1: gmaj" {  } { { "gmaj.bdf" "" { Schematic "F:/vhdl traffic light/traffic gmaj/gmaj.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CLK " "Info: Elaborating entity \"CLK\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "37 " "Info: Implemented 37 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "34 " "Info: Implemented 34 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "158 " "Info: Allocated 158 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 15 17:00:44 2008 " "Info: Processing ended: Mon Dec 15 17:00:44 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}