gmaj.map.qmsg

vhdl实现交通灯设计,可以实现十字路口处交通控制,开发工具quartus

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLK CLK:inst " "Info: Elaborating entity \"CLK\" for hierarchy \"CLK:inst\"" {  } { { "gmaj.bdf" "inst" { Schematic "F:/vhdl traffic light/traffic gmaj/gmaj.bdf" { { 0 176 272 96 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cctr1 cctr1:inst2 " "Info: Elaborating entity \"cctr1\" for hierarchy \"cctr1:inst2\"" {  } { { "gmaj.bdf" "inst2" { Schematic "F:/vhdl traffic light/traffic gmaj/gmaj.bdf" { { 0 328 464 192 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|gmaj\|cctr1:inst2\|next_state 8 " "Info: State machine \"\|gmaj\|cctr1:inst2\|next_state\" contains 8 states" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|gmaj\|cctr1:inst2\|next_state " "Info: Selected Auto state machine encoding method for state machine \"\|gmaj\|cctr1:inst2\|next_state\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|gmaj\|cctr1:inst2\|next_state " "Info: Encoding result for state machine \"\|gmaj\|cctr1:inst2\|next_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "8 " "Info: Completed encoding using 8 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cctr1:inst2\|next_state.s7 " "Info: Encoded state bit \"cctr1:inst2\|next_state.s7\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cctr1:inst2\|next_state.s6 " "Info: Encoded state bit \"cctr1:inst2\|next_state.s6\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cctr1:inst2\|next_state.s5 " "Info: Encoded state bit \"cctr1:inst2\|next_state.s5\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cctr1:inst2\|next_state.s4 " "Info: Encoded state bit \"cctr1:inst2\|next_state.s4\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cctr1:inst2\|next_state.s3 " "Info: Encoded state bit \"cctr1:inst2\|next_state.s3\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cctr1:inst2\|next_state.s2 " "Info: Encoded state bit \"cctr1:inst2\|next_state.s2\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cctr1:inst2\|next_state.s1 " "Info: Encoded state bit \"cctr1:inst2\|next_state.s1\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "cctr1:inst2\|next_state.s0 " "Info: Encoded state bit \"cctr1:inst2\|next_state.s0\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|gmaj\|cctr1:inst2\|next_state.s0 00000000 " "Info: State \"\|gmaj\|cctr1:inst2\|next_state.s0\" uses code string \"00000000\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|gmaj\|cctr1:inst2\|next_state.s1 00000011 " "Info: State \"\|gmaj\|cctr1:inst2\|next_state.s1\" uses code string \"00000011\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|gmaj\|cctr1:inst2\|next_state.s2 00000101 " "Info: State \"\|gmaj\|cctr1:inst2\|next_state.s2\" uses code string \"00000101\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|gmaj\|cctr1:inst2\|next_state.s3 00001001 " "Info: State \"\|gmaj\|cctr1:inst2\|next_state.s3\" uses code string \"00001001\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|gmaj\|cctr1:inst2\|next_state.s4 00010001 " "Info: State \"\|gmaj\|cctr1:inst2\|next_state.s4\" uses code string \"00010001\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|gmaj\|cctr1:inst2\|next_state.s5 00100001 " "Info: State \"\|gmaj\|cctr1:inst2\|next_state.s5\" uses code string \"00100001\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|gmaj\|cctr1:inst2\|next_state.s6 01000001 " "Info: State \"\|gmaj\|cctr1:inst2\|next_state.s6\" uses code string \"01000001\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|gmaj\|cctr1:inst2\|next_state.s7 10000001 " "Info: State \"\|gmaj\|cctr1:inst2\|next_state.s7\" uses code string \"10000001\"" {  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "cctr1.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/cctr1.vhd" 12 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "8 " "Info: Inferred 8 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "display:inst3\|Div0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"display:inst3\|Div0\"" {  } { { "display.vhd" "Div0" { Text "F:/vhdl traffic light/traffic gmaj/display.vhd" 31 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "display:inst3\|Mod1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"display:inst3\|Mod1\"" {  } { { "display.vhd" "Mod1" { Text "F:/vhdl traffic light/traffic gmaj/display.vhd" 32 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "display:inst3\|Mod0 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"display:inst3\|Mod0\"" {  } { { "display.vhd" "Mod0" { Text "F:/vhdl traffic light/traffic gmaj/display.vhd" 30 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "display:inst3\|Div1 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"display:inst3\|Div1\"" {  } { { "display.vhd" "Div1" { Text "F:/vhdl traffic light/traffic gmaj/display.vhd" 33 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "display:inst3\|Mod3 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"display:inst3\|Mod3\"" {  } { { "display.vhd" "Mod3" { Text "F:/vhdl traffic light/traffic gmaj/display.vhd" 36 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "display:inst3\|Div2 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"display:inst3\|Div2\"" {  } { { "display.vhd" "Div2" { Text "F:/vhdl traffic light/traffic gmaj/display.vhd" 35 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "display:inst3\|Mod2 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"display:inst3\|Mod2\"" {  } { { "display.vhd" "Mod2" { Text "F:/vhdl traffic light/traffic gmaj/display.vhd" 34 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "display:inst3\|Div3 lpm_divide " "Info: Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"display:inst3\|Div3\"" {  } { { "display.vhd" "Div3" { Text "F:/vhdl traffic light/traffic gmaj/display.vhd" 37 -1 0 } }  } 0 0 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf" 118 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "display:inst3\|lpm_divide:Div0 " "Info: Elaborated megafunction instantiation \"display:inst3\|lpm_divide:Div0\"" {  } { { "display.vhd" "" { Text "F:/vhdl traffic light/traffic gmaj/display.vhd" 31 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_djo.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_djo.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_djo " "Info: Found entity 1: lpm_divide_djo" {  } { { "db/lpm_divide_djo.tdf" "" { Text "F:/vhdl traffic light/traffic gmaj/db/lpm_divide_djo.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/abs_divider_cag.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/abs_divider_cag.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 abs_divider_cag " "Info: Found entity 1: abs_divider_cag" {  } { { "db/abs_divider_cag.tdf" "" { Text "F:/vhdl traffic light/traffic gmaj/db/abs_divider_cag.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_eoe.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_eoe.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_eoe " "Info: Found entity 1: alt_u_div_eoe" {  } { { "db/alt_u_div_eoe.tdf" "" { Text "F:/vhdl traffic light/traffic gmaj/db/alt_u_div_eoe.tdf" 34 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_3dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_3dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_3dc " "Info: Found entity 1: add_sub_3dc" {  } { { "db/add_sub_3dc.tdf" "" { Text "F:/vhdl traffic light/traffic gmaj/db/add_sub_3dc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_4dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_4dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_4dc " "Info: Found entity 1: add_sub_4dc" {  } { { "db/add_sub_4dc.tdf" "" { Text "F:/vhdl traffic light/traffic gmaj/db/add_sub_4dc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_5dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_5dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_5dc " "Info: Found entity 1: add_sub_5dc" {  } { { "db/add_sub_5dc.tdf" "" { Text "F:/vhdl traffic light/traffic gmaj/db/add_sub_5dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_6dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_6dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_6dc " "Info: Found entity 1: add_sub_6dc" {  } { { "db/add_sub_6dc.tdf" "" { Text "F:/vhdl traffic light/traffic gmaj/db/add_sub_6dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_7dc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_7dc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_7dc " "Info: Found entity 1: add_sub_7dc" {  } { { "db/add_sub_7dc.tdf" "" { Text "F:/vhdl traffic light/traffic gmaj/db/add_sub_7dc.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}