gmaj.map.rpt

vhdl实现交通灯设计,可以实现十字路口处交通控制,开发工具quartus

; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM Block Balancing                                                       ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                     ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                     ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------+
; CLK.vhd                          ; yes             ; User VHDL File                     ; F:/vhdl traffic light/traffic gmaj/CLK.vhd                       ;
; display.vhd                      ; yes             ; User VHDL File                     ; F:/vhdl traffic light/traffic gmaj/display.vhd                   ;
; cctr1.vhd                        ; yes             ; User VHDL File                     ; F:/vhdl traffic light/traffic gmaj/cctr1.vhd                     ;
; gmaj.bdf                         ; yes             ; User Block Diagram/Schematic File  ; F:/vhdl traffic light/traffic gmaj/gmaj.bdf                      ;
; lpm_divide.tdf                   ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf      ;
; abs_divider.inc                  ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/abs_divider.inc     ;
; sign_div_unsign.inc              ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/sign_div_unsign.inc ;
; aglobal72.inc                    ; yes             ; Megafunction                       ; c:/altera/72/quartus/libraries/megafunctions/aglobal72.inc       ;
; db/lpm_divide_djo.tdf            ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/lpm_divide_djo.tdf         ;
; db/abs_divider_cag.tdf           ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/abs_divider_cag.tdf        ;
; db/alt_u_div_eoe.tdf             ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/alt_u_div_eoe.tdf          ;
; db/add_sub_3dc.tdf               ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/add_sub_3dc.tdf            ;
; db/add_sub_4dc.tdf               ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/add_sub_4dc.tdf            ;
; db/add_sub_5dc.tdf               ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/add_sub_5dc.tdf            ;
; db/add_sub_6dc.tdf               ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/add_sub_6dc.tdf            ;
; db/add_sub_7dc.tdf               ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/add_sub_7dc.tdf            ;
; db/add_sub_8dc.tdf               ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/add_sub_8dc.tdf            ;
; db/lpm_abs_ui9.tdf               ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/lpm_abs_ui9.tdf            ;
; db/lpm_abs_2j9.tdf               ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/lpm_abs_2j9.tdf            ;
; db/add_sub_25f.tdf               ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/add_sub_25f.tdf            ;
; db/add_sub_u4f.tdf               ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/add_sub_u4f.tdf            ;
; db/lpm_divide_otl.tdf            ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/lpm_divide_otl.tdf         ;
; db/sign_div_unsign_hkh.tdf       ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/sign_div_unsign_hkh.tdf    ;
; db/alt_u_div_foe.tdf             ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/alt_u_div_foe.tdf          ;
; db/add_sub_9dc.tdf               ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/add_sub_9dc.tdf            ;
; db/add_sub_89c.tdf               ; yes             ; Auto-Generated Megafunction        ; F:/vhdl traffic light/traffic gmaj/db/add_sub_89c.tdf            ;
+----------------------------------+-----------------+------------------------------------+------------------------------------------------------------------+


+------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                ;
+---------------------------------------------+--------------+
; Resource                                    ; Usage        ;
+---------------------------------------------+--------------+
; Total logic elements                        ; 863          ;
;     -- Combinational with no register       ; 754          ;
;     -- Register only                        ; 22           ;
;     -- Combinational with a register        ; 87           ;
;                                             ;              ;
; Logic element usage by number of LUT inputs ;              ;
;     -- 4 input functions                    ; 173          ;
;     -- 3 input functions                    ; 221          ;
;     -- 2 input functions                    ; 300          ;
;     -- 1 input functions                    ; 147          ;
;     -- 0 input functions                    ; 0            ;
;                                             ;              ;
; Logic elements by mode                      ;              ;
;     -- normal mode                          ; 557          ;
;     -- arithmetic mode                      ; 306          ;
;     -- qfbk mode                            ; 0            ;
;     -- register cascade mode                ; 0            ;
;     -- synchronous clear/load mode          ; 24           ;
;     -- asynchronous clear/load mode         ; 48           ;