gmaj.map.rpt

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Analysis & Synthesis report for gmaj
Mon Dec 15 17:02:11 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |gmaj|cctr1:inst2|next_state
  8. General Register Statistics
  9. Inverted Register Statistics
 10. Multiplexer Restructuring Statistics (No Restructuring Performed)
 11. Parameter Settings for Inferred Entity Instance: display:inst3|lpm_divide:Div0
 12. Parameter Settings for Inferred Entity Instance: display:inst3|lpm_divide:Mod1
 13. Parameter Settings for Inferred Entity Instance: display:inst3|lpm_divide:Mod0
 14. Parameter Settings for Inferred Entity Instance: display:inst3|lpm_divide:Div1
 15. Parameter Settings for Inferred Entity Instance: display:inst3|lpm_divide:Mod3
 16. Parameter Settings for Inferred Entity Instance: display:inst3|lpm_divide:Div2
 17. Parameter Settings for Inferred Entity Instance: display:inst3|lpm_divide:Mod2
 18. Parameter Settings for Inferred Entity Instance: display:inst3|lpm_divide:Div3
 19. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Dec 15 17:02:11 2008    ;
; Quartus II Version          ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name               ; gmaj                                     ;
; Top-level Entity Name       ; gmaj                                     ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 863                                      ;
; Total pins                  ; 30                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 0                                        ;
; DSP block 9-bit elements    ; N/A until Partition Merge                ;
; Total PLLs                  ; 0                                        ;
; Total DLLs                  ; N/A until Partition Merge                ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP1C3T144C8        ;                    ;
; Top-level entity name                                                          ; gmaj               ; gmaj               ;
; Family name                                                                    ; Cyclone            ; Stratix II         ;
; Optimization Technique -- Cyclone                                              ; Speed              ; Balanced           ;
; Use Generated Physical Constraints File                                        ; Off                ;                    ;
; Use smart compilation                                                          ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation                            ; 1                  ; 1                  ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; Parallel Synthesis                                                             ; Off                ; Off                ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;