traffic.map.rpt

vhdl实现交通灯设计,可以实现十字路口处交通控制,开发工具quartus

; counter.vhd                      ; yes             ; User VHDL File  ; F:/vhdl traffic light/traffic/counter.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------------------+


+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary             ;
+---------------------------------------------+-----------+
; Resource                                    ; Usage     ;
+---------------------------------------------+-----------+
; Total logic elements                        ; 15        ;
;     -- Combinational with no register       ; 6         ;
;     -- Register only                        ; 0         ;
;     -- Combinational with a register        ; 9         ;
;                                             ;           ;
; Logic element usage by number of LUT inputs ;           ;
;     -- 4 input functions                    ; 4         ;
;     -- 3 input functions                    ; 1         ;
;     -- 2 input functions                    ; 6         ;
;     -- 1 input functions                    ; 4         ;
;     -- 0 input functions                    ; 0         ;
;                                             ;           ;
; Logic elements by mode                      ;           ;
;     -- normal mode                          ; 10        ;
;     -- arithmetic mode                      ; 5         ;
;     -- qfbk mode                            ; 0         ;
;     -- register cascade mode                ; 0         ;
;     -- synchronous clear/load mode          ; 6         ;
;     -- asynchronous clear/load mode         ; 6         ;
;                                             ;           ;
; Total registers                             ; 9         ;
; Total logic cells in carry chains           ; 6         ;
; I/O pins                                    ; 12        ;
; Maximum fan-out node                        ; Equal0~57 ;
; Maximum fan-out                             ; 9         ;
; Total fan-out                               ; 77        ;
; Average fan-out                             ; 2.85      ;
+---------------------------------------------+-----------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |counter                   ; 15 (15)     ; 9            ; 0           ; 12   ; 0            ; 6 (6)        ; 0 (0)             ; 9 (9)            ; 6 (6)           ; 0 (0)      ; |counter            ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+---------------------------------------------------------------------------+
; State Machine - |counter|current_state                                    ;
+------------------+------------------+------------------+------------------+
; Name             ; current_state.s2 ; current_state.s1 ; current_state.s0 ;
+------------------+------------------+------------------+------------------+
; current_state.s0 ; 0                ; 0                ; 0                ;
; current_state.s1 ; 0                ; 1                ; 1                ;
; current_state.s2 ; 1                ; 0                ; 1                ;
+------------------+------------------+------------------+------------------+


+------------------------------------------------------+-------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 9     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 6     ;
; Number of registers using Asynchronous Clear ; 6     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 6     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (No Restructuring Performed)                                                                          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+
; 4:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; No         ; |counter1|current_state.s0~0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sun Dec 14 18:03:50 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic
Info: Found 1 design units, including 1 entities, in source file traffic.bdf
    Info: Found entity 1: traffic
Info: Found 2 design units, including 1 entities, in source file counter.vhd
    Info: Found design unit 1: counter-ctr
    Info: Found entity 1: counter
Info: Found 2 design units, including 1 entities, in source file counter1.vhd
    Info: Found design unit 1: counter1-ctr
    Info: Found entity 1: counter1
Info: Found 2 design units, including 1 entities, in source file display.vhd
    Info: Found design unit 1: display-ctr
    Info: Found entity 1: display
Info: Found 2 design units, including 1 entities, in source file CLK.vhd
    Info: Found design unit 1: CLK-ctr
    Info: Found entity 1: CLK
Info: Elaborating entity "counter1" for the top level hierarchy
Info: State machine "|counter1|current_state" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|counter1|current_state"
Info: Encoding result for state machine "|counter1|current_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "current_state.s2"
        Info: Encoded state bit "current_state.s1"
        Info: Encoded state bit "current_state.s0"
    Info: State "|counter1|current_state.s0" uses code string "000"
    Info: State "|counter1|current_state.s1" uses code string "011"
    Info: State "|counter1|current_state.s2" uses code string "101"
Info: Implemented 26 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 9 output pins
    Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 158 megabytes of memory during processing
    Info: Processing ended: Sun Dec 14 18:03:58 2008
    Info: Elapsed time: 00:00:08