📄 gmaj.qsf
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# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# The default values for assignments are stored in the file
# gmaj_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C3T144C8
set_global_assignment -name TOP_LEVEL_ENTITY gmaj
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:13:03 DECEMBER 14, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name VHDL_FILE CLK.vhd
set_global_assignment -name VHDL_FILE counter.vhd
set_global_assignment -name VHDL_FILE counter1.vhd
set_global_assignment -name VHDL_FILE display.vhd
set_global_assignment -name BDF_FILE traffic.bdf
set_location_assignment PIN_27 -to clk
set_location_assignment PIN_60 -to hold
set_location_assignment PIN_61 -to reset
set_location_assignment PIN_111 -to ct[0]
set_location_assignment PIN_110 -to ct[1]
set_location_assignment PIN_109 -to ct[2]
set_location_assignment PIN_131 -to ct[3]
set_location_assignment PIN_133 -to ledb[1]
set_location_assignment PIN_132 -to ledb[0]
set_location_assignment PIN_134 -to ledb[2]
set_location_assignment PIN_139 -to leda[0]
set_location_assignment PIN_140 -to leda[1]
set_location_assignment PIN_141 -to leda[2]
set_location_assignment PIN_122 -to seg[0]
set_location_assignment PIN_121 -to seg[1]
set_location_assignment PIN_120 -to seg[2]
set_location_assignment PIN_119 -to seg[3]
set_location_assignment PIN_114 -to seg[4]
set_location_assignment PIN_113 -to seg[5]
set_location_assignment PIN_112 -to seg[6]
set_global_assignment -name VHDL_FILE counter2.vhd
set_global_assignment -name VHDL_FILE counter3.vhd
set_global_assignment -name VHDL_FILE cctr.vhd
set_global_assignment -name VHDL_FILE cctr1.vhd
set_global_assignment -name BDF_FILE gmaj.bdf
set_location_assignment PIN_126 -to ledc[0]
set_location_assignment PIN_124 -to ledc[1]
set_location_assignment PIN_100 -to ledc[2]
set_location_assignment PIN_75 -to ledd[0]
set_location_assignment PIN_77 -to ledd[1]
set_location_assignment PIN_83 -to ledd[2]
set_location_assignment PIN_69 -to ct[4]
set_location_assignment PIN_67 -to ct[5]
set_location_assignment PIN_71 -to ct[6]
set_location_assignment PIN_73 -to ct[7]
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
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