manch_detestbench.txt

1553B曼彻斯特编解码程序,用于总线通信

module manch_de(rst,clk16x,mdi,
                rdn,dout,data_ready) ;

input rst ;
input clk16x ;
input mdi ;
input rdn ;
output [7:0] dout ;
output data_ready ;
reg clk1x_enable ;
reg mdi1 ;
reg mdi2 ;
reg [7:0] dout ;
reg [3:0] no_bits_rcvd ;
reg [3:0] clkdiv  ;
reg data_ready ;
wire clk1x ;
reg nrz ;
wire sample ;
reg [7:0] rsr ;

always @(posedge clk16x or posedge rst) 
begin
if (rst)
begin
mdi1 <= 1'b0 ;
mdi2 <= 1'b0 ;
end
else
begin
mdi2 <= mdi1 ;
mdi1 <= mdi ;
end
end


always @(posedge clk16x or posedge rst)
begin
if (rst)
clk1x_enable <= 1'b0 ;
else if (!mdi1 && mdi2)
clk1x_enable <= 1'b1 ;
else if (!mdi1 && !mdi2 && no_bits_rcvd == 4'b1000)
clk1x_enable <= 1'b0 ;
end

assign sample = (!clkdiv[3] && !clkdiv[2] && clkdiv[1] && clkdiv[0]) || (clkdiv[3] && clkdiv[2] && !clkdiv[1] && !clkdiv[0]) ;

always @(posedge clk16x or posedge rst)
if (rst)
nrz = 1'b0 ;
else
if (no_bits_rcvd > 0 && sample == 1'b1)
nrz = mdi2 ^ clk1x ;

always @(posedge clk16x or posedge rst)
begin
if (rst)
clkdiv = 4'b0 ;
else if (clk1x_enable)
clkdiv = clkdiv + 1 ;
end

assign clk1x = clkdiv[3] ;

always @(posedge clk1x or posedge rst)
if (rst)
begin
rsr <= 8'h0 ;
end
else begin
rsr[7:1] <= rsr[6:0] ;
rsr[0] <= nrz ;
end

always @(posedge clk1x or posedge rst)
if (rst)
begin
dout <= 8'h0 ;
end
else begin
dout <= rsr ;
end

always @(posedge clk1x or posedge rst or negedge clk1x_enable)
begin
if (rst)
no_bits_rcvd = 4'b0000 ;
else if (!clk1x_enable)
begin
no_bits_rcvd = 4'b0000 ;
end
else
no_bits_rcvd = no_bits_rcvd + 1 ;
end

always @(negedge clk1x_enable or posedge rst)
begin
if (rst)
data_ready <= 1'b0 ;
else  if (!rdn)
data_ready <= 1'b0 ;
else
data_ready <= 1'b1 ;
end

endmodule