📄 manch_en_testbench.txt
字号:
`timescale 1 ns / 1 ns
module manch_en_testbench ;
reg [7:0] din ;
reg rst ;
reg clk ;
reg wr ;
wire mdo ;
wire ready ;
manch_en u1(.rst ( rst ),
.clk16x( clk ),
.wrn ( wr ),
.din ( din ),
.tbre ( ready),
.mdo ( mdo )
) ;
initial begin
rst = 1'b0 ;
clk = 1'b0 ;
din = 8'h0 ;
wr = 1'b0 ;
end
integer me_chann ;
initial begin
me_chann = $fopen("manch_en.rpt");
$fdisplay (me_chann,"\nSimulation of Manchester encoder Start.");
$timeformat(-9,,,5) ;
end
parameter clock_period = 10 ,
setup_time = clock_period/4 ;
always #(clock_period/2) clk = ~clk ;
initial begin
$fmonitor(me_chann,"rst=%b,wr=%b,din=%h,mdo=%b,ready=%b",rst,wr,din,mdo,ready);
#5 rst = 1'b1;
#15 rst = 1'b0 ;
#(3 * clock_period - setup_time) din = 8'hff ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(20 * clock_period) din = 8'haa ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(20 * clock_period) din = 8'h00 ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(20 * clock_period) din = 8'hf0 ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(20 * clock_period) din = 8'h0f ;
#(1 * clock_period) wr = 1'b1 ;
#(1 * clock_period) wr = 1'b0 ;
#(100 * clock_period) ;
$fdisplay (me_chann,"\nSimulation of Manchester encoder complete.");
$finish ;
end
endmodule
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -