lab32.v

来自「4對2解碼器 利用CASE方式來做選擇 較類似C語言」· Verilog 代码 · 共 66 行

module lab32(sel,sela, selb, selc, seld, i, j, out,a,b,c,d);
input [0:31]i;
input [0:3]j;
input [2:0]sel;
input [7:0]sela, selb, selc, seld;
output out,a,b,c,d;
reg out,a,b,c,d;
//4*1
always @(sel or j[0] or j[1] or j[2] or j[3])
	  case(sel)
		  2'b00: a=1;
		  2'b01: b=1;
		  2'b10: c=1;
		  2'b11: d=1;		  
  	 endcase
//8*1(a)
always @(a)
	  case(sela)
		  3'b000: out = i[0];
		  3'b001: out = i[1];
		  3'b010: out = i[2];
		  3'b011: out = i[3];
		  3'b100: out = i[4];
		  3'b101: out = i[5];
		  3'b110: out = i[6];
		  3'b111: out = i[7];
  	 endcase

//8*1(b)
always @(b)
	  case(selb)
		  3'b000: out = i[8];
		  3'b001: out = i[9];
		  3'b010: out = i[10];
		  3'b011: out = i[11];
		  3'b100: out = i[12];
		  3'b101: out = i[13];
		  3'b110: out = i[14];
		  3'b111: out = i[15];
  	 endcase
//8*1(c)
always @(c)
	  case(selc)
		  3'b000: out = i[16];
		  3'b001: out = i[17];
		  3'b010: out = i[18];
		  3'b011: out = i[19];
		  3'b100: out = i[20];
		  3'b101: out = i[21];
		  3'b110: out = i[22];
		  3'b111: out = i[23];
  	 endcase
//8*1(d)
always @(d)
	  case(seld)
		  3'b000: out = i[24];
		  3'b001: out = i[25];
		  3'b010: out = i[26];
		  3'b011: out = i[27];
		  3'b100: out = i[28];
		  3'b101: out = i[29];
		  3'b110: out = i[30];
		  3'b111: out = i[31];
  	 endcase
endmodule