mux_8x1.v

来自「4對2解碼器 利用CASE方式來做選擇 較類似C語言」· Verilog 代码 · 共 18 行

module MUX_8X1(sel, i0, i1, i2, i3, i4, i5, i6, i7, out);
input [2:0]i0, i1, i2, i3, i4, i5, i6, i7;
input [2:0]sel;
output [2:0]out;
reg [2:0]out;
always @(sel or i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7)
	  case(sel)
		  3'b000: out = i0;
		  3'b001: out = i1;
		  3'b010: out = i2;
		  3'b011: out = i3;
		  3'b100: out = i4;
		  3'b101: out = i5;
		  3'b110: out = i6;
		  3'b111: out = i7;
  	 endcase
endmodule