adder.v

来自「加法器 可做4BIT的運算 用直接語言撰寫」· Verilog 代码 · 共 25 行

//Top level module
module adder(S, C4, A, B, C0);
input [3:0] A, B;
input C0;
output [3:0] S;
output C4;
wire C1, C2, C3; 	//Intermediate carries


//Instantiate the fulladder
fulladder FA0(S[0], C1, A[0], B[0], C0);
fulladder FA1(S[1], C2, A[1], B[1], C1);
fulladder FA2(S[2], C3, A[2], B[2], C2);
fulladder FA3(S[3], C4, A[3], B[3], C3);
endmodule

//Description of full adder
module fulladder(S, C, x, y, z);
input x, y, z;
output S, C;
//Define combinational logic circuit
assign C = { (x ^ y) & z } | (x & y);
assign S = x ^ y ^ z;
endmodule