adder2.tan.rpt

2位并行加法器初学者必看初步了解FPGA

Classic Timing Analyzer report for adder2
Sun Apr 19 14:33:25 2009
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 12.877 ns   ; b[0] ; co ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------+
; tpd                                                         ;
+-------+-------------------+-----------------+------+--------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To     ;
+-------+-------------------+-----------------+------+--------+
; N/A   ; None              ; 12.877 ns       ; b[0] ; co     ;
; N/A   ; None              ; 12.525 ns       ; a[1] ; co     ;
; N/A   ; None              ; 12.448 ns       ; b[1] ; co     ;
; N/A   ; None              ; 12.414 ns       ; b[0] ; sum[1] ;
; N/A   ; None              ; 12.062 ns       ; a[1] ; sum[1] ;
; N/A   ; None              ; 11.985 ns       ; b[1] ; sum[1] ;
; N/A   ; None              ; 11.697 ns       ; a[0] ; co     ;
; N/A   ; None              ; 11.460 ns       ; b[0] ; sum[0] ;
; N/A   ; None              ; 11.234 ns       ; a[0] ; sum[1] ;
; N/A   ; None              ; 10.558 ns       ; ci   ; co     ;
; N/A   ; None              ; 10.377 ns       ; ci   ; sum[1] ;
; N/A   ; None              ; 10.282 ns       ; a[0] ; sum[0] ;
; N/A   ; None              ; 10.169 ns       ; ci   ; sum[0] ;
+-------+-------------------+-----------------+------+--------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Sun Apr 19 14:33:24 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder2 -c adder2 --timing_analysis_only
Info: Longest tpd from source pin "b[0]" to destination pin "co" is 12.877 ns
    Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_37; Fanout = 5; PIN Node = 'b[0]'
    Info: 2: + IC(5.752 ns) + CELL(0.590 ns) = 7.817 ns; Loc. = LC_X1_Y9_N2; Fanout = 2; COMB Node = 'Mux2~3'
    Info: 3: + IC(0.436 ns) + CELL(0.590 ns) = 8.843 ns; Loc. = LC_X1_Y9_N9; Fanout = 1; COMB Node = 'Add0~148'
    Info: 4: + IC(1.910 ns) + CELL(2.124 ns) = 12.877 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'co'
    Info: Total cell delay = 4.779 ns ( 37.11 % )
    Info: Total interconnect delay = 8.098 ns ( 62.89 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Allocated 111 megabytes of memory during processing
    Info: Processing ended: Sun Apr 19 14:33:25 2009
    Info: Elapsed time: 00:00:01