adder2.map.summary

来自「2位并行加法器初学者必看初步了解FPGA」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Sun Apr 19 14:33:15 2009
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : adder2
Top-level Entity Name : adder2
Family : Cyclone
Total logic elements : 6
Total pins : 8
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : 0
Total DLLs : N/A until Partition Merge