adder2.hier_info

2位并行加法器初学者必看初步了解FPGA

|adder2
a[0] => Mux2.IN17
a[0] => Mux1.IN4
a[0] => Mux0.IN17
a[1] => Mux2.IN16
a[1] => Mux0.IN16
b[0] => Mux2.IN19
b[0] => Mux1.IN5
b[0] => Mux0.IN19
b[1] => Mux2.IN18
b[1] => Mux0.IN18
ci => sumtemp~2.OUTPUTSELECT
ci => sumtemp~1.OUTPUTSELECT
ci => sumtemp~0.OUTPUTSELECT
sum[0] <= sumtemp~2.DB_MAX_OUTPUT_PORT_TYPE
sum[1] <= sumtemp~1.DB_MAX_OUTPUT_PORT_TYPE
co <= sumtemp~0.DB_MAX_OUTPUT_PORT_TYPE