adder2.tan.qmsg

2位并行加法器初学者必看初步了解FPGA

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 19 14:33:24 2009 " "Info: Processing started: Sun Apr 19 14:33:24 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off adder2 -c adder2 --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adder2 -c adder2 --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[0\] co 12.877 ns Longest " "Info: Longest tpd from source pin \"b\[0\]\" to destination pin \"co\" is 12.877 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns b\[0\] 1 PIN PIN_37 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_37; Fanout = 5; PIN Node = 'b\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { b[0] } "NODE_NAME" } } { "adder2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/2位并行加法/adder2.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.752 ns) + CELL(0.590 ns) 7.817 ns Mux2~3 2 COMB LC_X1_Y9_N2 2 " "Info: 2: + IC(5.752 ns) + CELL(0.590 ns) = 7.817 ns; Loc. = LC_X1_Y9_N2; Fanout = 2; COMB Node = 'Mux2~3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.342 ns" { b[0] Mux2~3 } "NODE_NAME" } } { "adder2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/2位并行加法/adder2.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.590 ns) 8.843 ns Add0~148 3 COMB LC_X1_Y9_N9 1 " "Info: 3: + IC(0.436 ns) + CELL(0.590 ns) = 8.843 ns; Loc. = LC_X1_Y9_N9; Fanout = 1; COMB Node = 'Add0~148'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.026 ns" { Mux2~3 Add0~148 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.910 ns) + CELL(2.124 ns) 12.877 ns co 4 PIN PIN_27 0 " "Info: 4: + IC(1.910 ns) + CELL(2.124 ns) = 12.877 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'co'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.034 ns" { Add0~148 co } "NODE_NAME" } } { "adder2.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA/2位并行加法/adder2.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.779 ns ( 37.11 % ) " "Info: Total cell delay = 4.779 ns ( 37.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.098 ns ( 62.89 % ) " "Info: Total interconnect delay = 8.098 ns ( 62.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.877 ns" { b[0] Mux2~3 Add0~148 co } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.877 ns" { b[0] {} b[0]~out0 {} Mux2~3 {} Add0~148 {} co {} } { 0.000ns 0.000ns 5.752ns 0.436ns 1.910ns } { 0.000ns 1.475ns 0.590ns 0.590ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 19 14:33:25 2009 " "Info: Processing ended: Sun Apr 19 14:33:25 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}