adder2.vhd

来自「2位并行加法器初学者必看初步了解FPGA」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity adder2 is
   port(a,b:std_logic_vector(1 downto 0);
         ci:in std_logic;
         sum:out std_logic_vector(1 downto 0);
         co:out std_logic);
end adder2;

architecture one of adder2 is
   subtype romword is std_logic_vector(2 downto 0);
   type romtable is array (0 to 15) of romword;
   constant addertble:romtable:=
((b"000"),(b"001"),(b"010"),(b"011"),
 (b"001"),(b"010"),(b"011"),(b"100"),
 (b"010"),(b"011"),(b"100"),(b"101"),
 (b"011"),(b"100"),(b"101"),(b"110"));
 signal sumtemp:std_logic_vector(2 downto 0);
 begin
   process(a,b,ci)
   variable com:std_logic_vector(3 downto 0);
    begin
     com:=a&b;
     if(ci='1') then
     sumtemp<=addertble(conv_integer(com))+'1';
     else 
     sumtemp<=addertble(conv_integer(com));
    end if;
   end process;
 sum<=sumtemp(1 downto 0);
 co<=sumtemp(2);
end one;