top_vga.v

产生VGA彩条信号(Verilog 语言）

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:07:42 08/27/2008 
// Design Name: 
// Module Name:    vgatiming 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//,h_state,h_reset,h_blank,v_state,v_reset,v_blank,cblank
//////////////////////////////////////////////////////////////////////////////////
module vgatiming(clk_50m,h_syn,h_cnt,v_syn,v_cnt,r,g,b);

		input clk_50m;
		output r,g,b;
		output h_syn,v_syn,h_cnt,v_cnt;
		reg clk;
		reg h_syn;
		reg v_syn;
		reg [3:0] h_state;
		reg [3:0] v_state;
		reg [3:0] r;
		reg [3:0] g;
		reg [3:0] b;
		reg [11:0] h_cnt;
		reg [11:0] v_cnt;
		reg h_reset;
 


		
		parameter h_video = 4'b0001,
					 h_front = 4'b0010,
					 h_sync  = 4'b0100,
					 h_back  = 4'b1000;
		parameter v_video = 4'b0001,
		          v_front = 4'b0010,
					 v_sync  = 4'b0100,
					 v_back  = 4'b1000;
		initial
			begin
				v_syn <= 1;
				h_syn <= 1;
				h_reset <= 0;
				h_state <= h_video;
				h_cnt <= 11'd0;
				v_state <= v_video;
				v_cnt <= 11'd0;
				clk <= 0;
			end
		always @ (posedge clk_50m) 
		begin
			clk=~clk;
		end
		always @ (posedge clk)
		begin

					case(h_state)
					h_video:
						begin
						if(h_cnt==11'd639)
							begin
							
							h_state <= h_front;
							h_cnt <= h_cnt+1;
							end
						else h_cnt <= h_cnt+1;
						end
					h_front:
						begin
						if(h_cnt==11'd663)
							begin
							h_reset <=0;
							h_state <= h_sync;
							h_cnt <= h_cnt+1;
							h_syn <= 0;
							end
						else h_cnt <= h_cnt+1;
						end
					h_sync:
						begin
						if(h_cnt==11'd759)
							begin
							h_state <= h_back;
							h_cnt <= h_cnt+1;
							h_syn <= 1;
							end
						else h_cnt <= h_cnt+1;
						end
					h_back:
						begin
						if(h_cnt==11'd799)
							begin
							h_reset <= 1;
							h_state <= h_video;
							h_syn <= 1;
							h_cnt <= 11'd0;
							end
						else h_cnt <= h_cnt+1;
						end
					default:h_reset <= 1;
					endcase
		end
		
		always @ (posedge h_reset)
		begin

			case(v_state)
					v_video:
						begin
						if(v_cnt==11'd479)
							begin
							v_state <= v_front;
							v_cnt <= v_cnt+1;

							end
						else v_cnt <= v_cnt+1;
						end
					v_front:
						begin
						if(v_cnt==11'd497)
							begin
							v_state <= v_sync;
							v_cnt <= v_cnt+1;
							v_syn <=0;
							end
						else v_cnt <= v_cnt+1;
						end
					v_sync:
						begin
						if(v_cnt==11'd499)
							begin
							v_state <= v_back;
							v_cnt <= v_cnt+1;
							v_syn <= 1;
							end
						else v_cnt <= v_cnt+1;
						end
					v_back:
						begin
						if(v_cnt==11'd524)
							begin
							v_state <= v_video;
							v_cnt <= 0;
							end
						else v_cnt <= v_cnt+1;
						end
					default:v_state <= v_video;
					endcase
		end


		always @ (posedge clk)
			begin
				if(h_cnt< 11'd100)
					begin
					r = 4'b1111;
					g = 4'b0000;
					b = 4'b0000;
					end
				else if(h_cnt<11'd200)
					begin
					r = 4'b0000;
					g = 4'b1111;
					b = 4'b0000;
					end
				else if(h_cnt<11'd300)
					begin
					r = 4'b0000;
					g = 4'b0000;
					b = 4'b1111;
					end
				else if(h_cnt<11'd400)
					begin
					r = 4'b1111;
					g = 4'b1111;
					b = 4'b0000;
					end
				else 
					begin
					r = 4'b1111;
					g = 4'b0000;
					b = 4'b1111;
					end
			end
			

					
		


endmodule