idm.v

Free 8051 core upload

//**************************************************************************//
// Copyright (c) 1999-2005  Digital Core Design  DCD s.c.                   //
//**************************************************************************//
// Please review the terms of the license agreement before using this file. //
// If you are not an authorized user, please destroy this source code file  //
// and notify DCD s.c. immediately that you inadvertently received an       //
// unauthorized copy.                                                       //
//**************************************************************************//
//////////////////////////////////////////////////////////////////////////////
// File name            : IDM.V
// File contents        : Module IDM
// Purpose              : Synchronous Random Access Memory
//                        Dedicated to use as DP8051/DP0390
//                        Internal Data Memory
// Technology           : Stratix, Cyclone, Stratix2, Cyclone2
// Version              : 4.00
//////////////////////////////////////////////////////////////////////////////

module idm(clk, we, addr, din, dout);

input        clk;
input        we;
input  [5:0] addr;
input  [7:0] din;
output [7:0] dout;

reg    [5:0] addr_reg;
reg    [7:0] din_reg;
reg          we_reg;
reg          data_sel_reg;
wire   [7:0] q_s;

always @(posedge clk)
begin
  addr_reg <= addr;
  din_reg <= din;
  we_reg <= we;
end

always @(posedge clk)
begin
  if (we_reg==1'b1 && addr_reg==addr)
    data_sel_reg <= 1'b1;
  else
    data_sel_reg <= 1'b0;
end

ALTSYNCRAM lpm_instance
  (.clock0    (clk),
   .wren_a    (we_reg),
   .address_a (addr_reg),
   .data_a    (din),
   .address_b (addr),
   .q_b       (q_s)
   );

assign dout = (data_sel_reg==1'b1 ? din_reg : q_s);

defparam	lpm_instance.ADDRESS_ACLR_A = "NONE";
defparam	lpm_instance.ADDRESS_ACLR_B = "NONE";
defparam	lpm_instance.ADDRESS_REG_B = "CLOCK0";
defparam	lpm_instance.BYTE_SIZE = 8;
defparam	lpm_instance.BYTEENA_ACLR_A = "NONE";
defparam	lpm_instance.BYTEENA_ACLR_B = "NONE";
defparam	lpm_instance.BYTEENA_REG_B = "CLOCK0";
defparam	lpm_instance.INDATA_ACLR_A = "NONE";
defparam	lpm_instance.INDATA_ACLR_B = "NONE";
defparam	lpm_instance.INDATA_REG_B = "CLOCK0";
defparam	lpm_instance.INIT_FILE = "UNUSED";
defparam	lpm_instance.INIT_FILE_LAYOUT = "PORT_A";
defparam	lpm_instance.MAXIMUM_DEPTH = 0;
defparam	lpm_instance.NUMWORDS_A = 64;
defparam	lpm_instance.NUMWORDS_B = 64;
defparam	lpm_instance.OPERATION_MODE = "DUAL_PORT";
defparam	lpm_instance.OUTDATA_ACLR_A = "NONE";
defparam	lpm_instance.OUTDATA_ACLR_B = "NONE";
defparam	lpm_instance.OUTDATA_REG_A = "UNREGISTERED";
defparam	lpm_instance.OUTDATA_REG_B = "UNREGISTERED";
defparam	lpm_instance.RAM_BLOCK_TYPE = "AUTO";
defparam	lpm_instance.RDCONTROL_ACLR_B = "NONE";
defparam	lpm_instance.RDCONTROL_REG_B = "CLOCK0";
defparam	lpm_instance.READ_DURING_WRITE_MODE_MIXED_PORTS = "DONT_CARE";
defparam	lpm_instance.WIDTH_A = 8;
defparam	lpm_instance.WIDTH_B = 8;
defparam	lpm_instance.WIDTH_BYTEENA_A = 1;
defparam	lpm_instance.WIDTH_BYTEENA_B = 1;
defparam	lpm_instance.WIDTHAD_A = 6;
defparam	lpm_instance.WIDTHAD_B = 6;
defparam	lpm_instance.WRCONTROL_ACLR_A = "NONE";
defparam	lpm_instance.WRCONTROL_ACLR_B = "NONE";
defparam	lpm_instance.WRCONTROL_WRADDRESS_REG_B = "CLOCK0";

endmodule