example.qsf

Free 8051 core upload

 
# Project-Wide Assignments
# ========================
set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP1"
 
# Pin & Location Assignments
# ==========================
set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
 
# Timing Assignments
# ==================
set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF
 
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name CASCADE_CHAIN_LENGTH 4
set_global_assignment -name AUTO_PACKED_REGISTERS NORMAL
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name AUTO_ROM_RECOGNITION OFF
set_global_assignment -name AUTO_RAM_RECOGNITION OFF
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS OFF
set_global_assignment -name IGNORE_LCELL_BUFFERS OFF
set_global_assignment -name IGNORE_CASCADE_BUFFERS OFF
set_global_assignment -name IGNORE_CARRY_BUFFERS OFF
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name FAMILY "Stratix II"
set_global_assignment -name TOP_LEVEL_ENTITY example
 
# Fitter Assignments
# ==================
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF
set_global_assignment -name DEVICE AUTO
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
 
# Timing Analysis Assignments
# ===========================
set_global_assignment -name MAX_SCC_SIZE 50
 
# SignalTap II Assignments
# ========================
set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
 
# ----------------
# start CLOCK(clk)
 
	# Timing Assignments
	# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id clk
set_global_assignment -name FMAX_REQUIREMENT "150 MHz" -section_id clk
 
# end CLOCK(clk)
# --------------
 
# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)
 
	# Analysis & Synthesis Assignments
	# ================================
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
 
# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------
 
# --------------------------
# start ENTITY(example)
 
	# Timing Assignments
	# ==================
set_instance_assignment -name CLOCK_SETTINGS clk -to clk
 
# end ENTITY(example)
# --------------------------
 

set_global_assignment -name TSU_REQUIREMENT "2 ns"
set_global_assignment -name TCO_REQUIREMENT "8 ns"
set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to xaddress
set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to xdata
set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to xdatard
set_instance_assignment -name OUTPUT_PIN_LOAD 10 -to xdatawr
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name OPTIMIZE_TIMING "EXTRA EFFORT"
set_global_assignment -name VQM_FILE dp8051.vqm
set_global_assignment -name VERILOG_FILE rom.v
set_global_assignment -name VERILOG_FILE idm.v
set_global_assignment -name VERILOG_FILE readyctrl.v
set_global_assignment -name VERILOG_FILE example.v