rom.v

Free 8051 core upload

//**************************************************************************//
// Copyright (c) 1999-2003  Digital Core Design  DCD s.c.                   //
//**************************************************************************//
// Please review the terms of the license agreement before using this file. //
// If you are not an authorized user, please destroy this source code file  //
// and notify DCD s.c. immediately that you inadvertently received an       //
// unauthorized copy.                                                       //
//**************************************************************************//
//////////////////////////////////////////////////////////////////////////////
// File name            : ROM.V
// File contents        : Module ROM
// Purpose              : Synchronous Read Only Memory
// Technology           : STRATIX, CYCLONE
// Version              : 2.00
//////////////////////////////////////////////////////////////////////////////

module rom(clk, addr, dout);

input        clk;
input  [9:0] addr;
output [7:0] dout;

ALTSYNCRAM lpm_instance
  (.clock0    (clk),
   .address_a (addr),
   .q_a       (dout)
   );


defparam	lpm_instance.ADDRESS_ACLR_A = "NONE";
defparam	lpm_instance.ADDRESS_ACLR_B = "NONE";
defparam	lpm_instance.ADDRESS_REG_B = "CLOCK0";
defparam	lpm_instance.BYTE_SIZE = 8;
defparam	lpm_instance.BYTEENA_ACLR_A = "NONE";
defparam	lpm_instance.BYTEENA_ACLR_B = "NONE";
defparam	lpm_instance.BYTEENA_REG_B = "CLOCK0";
defparam	lpm_instance.INDATA_ACLR_A = "NONE";
defparam	lpm_instance.INDATA_ACLR_B = "NONE";
defparam	lpm_instance.INDATA_REG_B = "CLOCK0";
defparam	lpm_instance.INIT_FILE = "rom.hex";
defparam	lpm_instance.INIT_FILE_LAYOUT = "PORT_A";
defparam	lpm_instance.MAXIMUM_DEPTH = 0;
defparam	lpm_instance.NUMWORDS_A = 1024;
defparam	lpm_instance.NUMWORDS_B = 1024;
defparam	lpm_instance.OPERATION_MODE = "SINGLE_PORT";
defparam	lpm_instance.OUTDATA_ACLR_A = "NONE";
defparam	lpm_instance.OUTDATA_ACLR_B = "NONE";
defparam	lpm_instance.OUTDATA_REG_A = "UNREGISTERED";
defparam	lpm_instance.OUTDATA_REG_B = "UNREGISTERED";
defparam	lpm_instance.RAM_BLOCK_TYPE = "AUTO";
defparam	lpm_instance.RDCONTROL_ACLR_B = "NONE";
defparam	lpm_instance.RDCONTROL_REG_B = "CLOCK0";
defparam	lpm_instance.READ_DURING_WRITE_MODE_MIXED_PORTS = "DONT_CARE";
defparam	lpm_instance.WIDTH_A = 8;
defparam	lpm_instance.WIDTH_B = 8;
defparam	lpm_instance.WIDTH_BYTEENA_A = 1;
defparam	lpm_instance.WIDTH_BYTEENA_B = 1;
defparam	lpm_instance.WIDTHAD_A = 10;
defparam	lpm_instance.WIDTHAD_B = 10;
defparam	lpm_instance.WRCONTROL_ACLR_A = "NONE";
defparam	lpm_instance.WRCONTROL_ACLR_B = "NONE";
defparam	lpm_instance.WRCONTROL_WRADDRESS_REG_B = "CLOCK0";

endmodule