dp32_types.vhd

DLX CPU VHDL CODE UNIVERSITY

library ieee;

use ieee.std_logic_1164.all;

--
--  File:	$RCSfile: dp32_types.vhd,v $
--  Revision:	$Revision: 1.9 $
--  Author:	$Author: petera $
--  Date:	$Date: 90/06/22 12:37:25 $
--

package dp32_types is

  constant unit_delay : Time := 1 ns;
  
  type bool_to_bit_table is array (boolean) of bit;

  constant bool_to_bit : bool_to_bit_table;

  subtype bit_96 is bit_vector(95 downto 0);

  subtype bit_32 is bit_vector(31 downto 0);
  type bit_32_array is array (integer range <>) of bit_32;
  function resolve_bit_32 (driver : in bit_32_array) return bit_32;
  subtype bus_bit_32 is resolve_bit_32 bit_32;

  subtype bit_56 is bit_vector(55 downto 0);
  subtype bit_27 is bit_vector(26 downto 0);
  subtype bit_55 is bit_vector(54 downto 0);
  subtype bit_24 is bit_vector(23 downto 0);
  subtype bit_53 is bit_vector(52 downto 0);
  subtype bit_64 is bit_vector(63 downto 0);
  subtype bit_52 is bit_vector(51 downto 0);
  subtype bit_11 is bit_vector(10 downto 0);
  subtype bit_23 is bit_vector(22 downto 0);  
  subtype bit_6 is bit_vector(5 downto 0);
  subtype bit_16 is bit_vector (15 downto 0);
  subtype bit_26 is bit_vector (25 downto 0);
  subtype bit_5 is bit_vector (4 downto 0);
  subtype bit_2 is bit_vector (1 downto 0);
  subtype bit_4 is bit_vector (3 downto 0);
  subtype bit_8 is bit_vector (7 downto 0);  
  subtype bit_7 is bit_vector (6 downto 0);  
  subtype bit_3 is bit_vector (2 downto 0);
  subtype bit_1 is bit_vector (0 downto 0);

  subtype CC_bits is bit_vector(2 downto 0);
  subtype cm_bits is bit_vector(3 downto 0);



  -- assume twos compliment integers:

  function bits_to_int (bits : in bit_vector) return integer;

  function bits_to_uint (bits : in bit_vector) return integer;

--  function bool_to_bit (b : in boolean ) return bit;
  
  function bits_to_natural (bits : in bit_vector) return natural;
 
  function add ( bits : in bit_vector; num : in natural) return bit_vector; 

  function bit_to_vector ( b: in bit) return bit_vector; 

  function bits_or ( b1,b2 : in bit_vector) return bit_vector; 

  function vector_to_string (bits : in bit_vector) return string;

  function bit_to_std_logic (b: in bit) return std_logic;
  
  procedure int_to_bits (int : in integer; bits : out bit_vector);
  
  FUNCTION twos_complement(bv_in: in bit_vector) RETURN bit_vector;
  
  procedure natural_to_bits (n : in natural; bits : out bit_vector); 

  function power (x , p : in natural) return natural;

end dp32_types;

package body dp32_types is

  constant bool_to_bit : bool_to_bit_table :=
    (false => '0', true => '1');

  function resolve_bit_32 (driver : in bit_32_array) return bit_32 is
    constant float_value : bit_32 := X"0000_0000";
    variable result : bit_32 := float_value;
  begin
    for i in driver'range loop
      result := result or driver(i);
    end loop;
    return result;
  end resolve_bit_32;

  function power (x , p : in natural) return natural is
  variable r: natural :=x;
  variable i: natural :=0;
  begin
    for i in p downto 1 loop
      r:=r*x;
    end loop;

  return r;
  end power;


  function bit_to_vector ( b: in bit) return bit_vector is 
	variable r:bit_1;
  begin
        r(0):=b;
  return r;
  end bit_to_vector;

  function bits_to_int (bits : in bit_vector) return integer is
    variable temp : bit_vector(bits'range);
    variable result : integer := 0;
  begin
    if bits(bits'left) = '1' then	  -- negative number
      temp := not bits;
    else
      temp := bits;
    end if;
    for index in bits'range loop	  -- sign bit of temp = '0'
      result := result * 2 + bit'pos(temp(index));
    end loop;
    if bits(bits'left) = '1' then
      result := (-result) - 1;
    end if;
    return result;
  end bits_to_int;

  function bits_to_uint (bits : in bit_vector) return integer is
    variable temp : bit_vector(bits'range);
    variable result : integer := 0;
  begin
   
      temp := bits;
   
    for index in bits'range loop	  -- sign bit of temp = '0'
      result := result * 2 + bit'pos(temp(index));
    end loop;

    return result;
  end bits_to_uint;

  function bits_to_natural (bits : in bit_vector) return natural is
    variable result : natural := 0;
  begin
    for index in bits'range loop
      result := result * 2 + bit'pos(bits(index));
    end loop;
    return result;
  end bits_to_natural;

  function add ( bits : in bit_vector; num : in natural) return bit_vector is 
    variable temp : natural;
    variable r : bit_vector(bits'range);
  begin
    temp:=bits_to_natural(bits);
    temp:=temp+num;
    natural_to_bits(temp,r);    
    return r;
  end add;
  

--  function bool_to_bit (b : in boolean ) return bit is
--	variable t : bit;
--  begin
--        if (b) then
--		t:='1';
--	else
--		t:='0';
--	end if;
--  return t;	
--  end bool_to_bit;



  function vector_to_string (bits : in bit_vector) return string is
	variable temp : string( bits'left+1 downto 1 );
  begin
	for i in bits'reverse_range loop
		if(bits(i)='0') then
			temp(i+1):='0';
	        else
			temp(i+1):='1';
		end if;

	end loop;
  return temp;
  end vector_to_string;




  procedure int_to_bits (int : in integer; bits : out bit_vector) is
    variable temp : integer;
    variable result : bit_vector(bits'range);
  begin
    if int < 0 then
      temp := -(int+1);
    else
      temp := int;
    end if;
    for index in bits'reverse_range loop
      result(index) := bit'val(temp rem 2);
      temp := temp / 2;
    end loop;
    if int < 0 then
      result := not result;
      result(bits'left) := '1';
    end if;
    bits := result;
  end int_to_bits;

  procedure natural_to_bits (n : in natural; bits : out bit_vector) is
    variable temp : natural;
    variable result : bit_vector(bits'range);
  begin
    if n < 0 then
      temp := -(n+1);
    else
      temp := n;
    end if;
    for index in bits'reverse_range loop
      result(index) := bit'val(temp rem 2);
      temp := temp /2;
    end loop;
    if n < 0 then
      result := not result;
      result(bits'left) := '1';
    end if;
    bits := result;
  end natural_to_bits;


  function bits_or ( b1,b2 : in bit_vector) return bit_vector is
  variable t1,t1b : bit_vector(b1'range);
  variable t2,t2b : bit_vector(b2'range);
  variable i1,i2 : integer;
  begin
  i1:=bits_to_uint(b1);
  i2:=bits_to_uint(b2);

  if (b1'high > b2'high ) then

  int_to_bits(i1,t1);
  int_to_bits(i2,t1b);
  t1:=t1 or t1b;
--  for i in b1'range loop
  --  t1(i):=b1(i);
  --end loop;
  --for i in b2'range loop
  --  if(b2(i)='1') then
  --     t1(i):='1';
  --  end if;
  --end loop;

  return t1;
  else
  int_to_bits(i1,t2);
  int_to_bits(i2,t2b);
  t2:=t2 or t2b;
  --for i in b2'range loop
  --  t2(i):=b2(i);
  --end loop;
  --for i in b1'range loop
  -- if(b1(i)='1') then
  --     t2(i):='1';
  --  end if;
  --end loop;

  return t2;
  end if;
  end bits_or;

  
FUNCTION twos_complement(bv_in: in bit_vector) RETURN bit_vector IS
    variable bv_out : bit_vector(bv_in'length-1 downto 0);
    variable i : integer;
    variable carry : boolean := true;
	
    BEGIN
	bv_out := NOT(bv_in);
	FOR i IN bv_in'reverse_range LOOP
	    IF carry THEN
		IF bv_out(i) = '0' THEN
		    bv_out(i) := '1';
		    carry := false;
		ELSE
		    bv_out(i) := '0';
		END IF;
	    END IF;
	END LOOP;		
	RETURN(bv_out);
    END twos_complement;	

  function bit_to_std_logic (b: in bit) return std_logic is
  --variable r: std_logic:=0;
  begin
  if (b='1') then
	return '1';
  end if;
  return '0';

  
  end bit_to_std_logic;

end dp32_types;